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6CCVD Research

Charge Trapping Analysis of High Speed Diamond FETs

At a Glance

Section titled ā€œAt a Glanceā€
MetadataDetails
Publication Date2017-02-06
JournalMRS Advances
AuthorsPankaj B. Shah, James Weil, A. Glen Birdwell, Tony Ivanov
InstitutionsDEVCOM Army Research Laboratory
Citations8

Abstract

Section titled ā€œAbstractā€

Abstract Charge carrier trapping in diamond surface conduction field effect transistors (FETs) has been analyzed. For these devices two methods were used to obtain a negative electron affinity diamond surface; either plasma hydrogenation or annealing in an H 2 environment. In both cases the Al 2 O 3 gate dielectric can trap both electrons and holes in deep energy levels with emission timescales of seconds, while the diamond - Al 2 O 3 interface traps exhibit much shorter time scales in the microsecond range. Capacitance-Voltage (CV) analysis indicates that these interface traps exhibit acceptor-like characteristics. Correlation with CV based free hole density measurements indicates that the conductance based interface trap analysis provides a method to quantify surface characteristics that lead to surface conduction in hydrogenated diamond where atmospheric adsorbates provide the acceptor states for transfer doping of the surface.

Tech Support

Section titled ā€œTech Supportā€

Original Source

Section titled ā€œOriginal Sourceā€

References

Section titled ā€œReferencesā€
  1. 2014 - Phys. Rev
  2. 2009 - Appl. Phys. Lett

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