Achieving micron-scale plasticity and theoretical strength in Silicon

At a Glance

Metadata	Details
Publication Date	2020-05-29
Journal	Nature Communications
Authors	Ming Chen, László Pethö, Alla S. Sologubenko, Huan Ma, Johann Michler
Institutions	ETH Zurich, Swiss Federal Laboratories for Materials Science and Technology
Citations	79
Analysis	Full AI Review Included

Executive Summary

This study demonstrates a breakthrough in silicon (Si) mechanical properties, achieving near-theoretical strength and micron-scale plasticity at ambient temperature through advanced surface engineering via lithography.

Near-Theoretical Strength: Lithographically processed Si micropillars achieved a critical resolved shear stress (T_CRSS) of approximately 4 GPa, approaching the theoretical ideal strength limit for Si (6.8 GPa).
Ultrahigh Elasticity: The pillars exhibited an ultrahigh uniaxial elastic strain limit of 6-7.5%, representing a 20-40% improvement over Si processed by conventional lithography or Focused Ion Beam (FIB) milling.
Micron-Scale Plasticity: Plastic deformation was observed in pillars up to 3.5 µm in diameter (achieving 0.3% plastic strain), extending the brittle-to-ductile transition (BDT) size by an order of magnitude compared to FIB-machined samples.
Surface Engineering Success: The superior performance is attributed to a multi-step wet cleaning and thermal oxidation process that removes fabrication damage and residual contamination, yielding a near-pristine, defect-scarce surface.
Weak Size Effect: Lithographic pillars displayed a very weak size effect exponent (n = 0.081), indicating that surface nucleation remains the dominant deformation mechanism even at larger scales.
Dislocation Mechanism Transition: The high stresses achieved enabled the first observation of a stress/size-dependent transition in dislocation behavior at ambient temperature, shifting from full dislocations (nanoscale) to partial dislocations (micron-scale).
Engineering Impact: This surface engineering pathway enables the fabrication of more robust Si-based MEMS/micro-devices and enhances functional properties via strain engineering.

Technical Specifications

Parameter	Value	Unit	Context
Maximum Shear Strength (T_CRSS)	~4	GPa	Achieved in lithographic Si pillars
Theoretical Ideal Shear Strength (DFT)	6.8	GPa	Density Functional Theory prediction
Maximum Elastic Strain Limit	6 - 7.5	%	Uniaxial compressive strain in lithographic pillars
Plasticity Limit Diameter (Lithography)	3.5	µm	Largest diameter showing 0.3% plastic strain
Plasticity Limit Diameter (FIB-milled)	< 0.5	µm	Pillars > 0.5 µm failed brittlely
Size Effect Exponent (n, Lithography)	0.081	N/A	T_CRSS = C D^-n; indicates weak size dependence
FIB Amorphous Layer Thickness	~40	nm	Damage layer observed on FIB-milled pillars
Si Shear Modulus (G₍₁₁₁₎/10)	6.69	GPa	Reference value for ideal strength
Crystalline Si Young’s Modulus (E)	127	GPa	(100)-oriented crystalline Si
Amorphous Si Young’s Modulus (E)	33.3	GPa	Amorphous layer reference
Microcompression Strain Rate	5 x 10^-4	s^-1	Constant strain rate used for testing
FIB Milling Voltage	30	kV	Ga⁺ focused ion beam used for comparison samples

Key Methodologies

The study relied on precise fabrication and advanced characterization techniques to isolate the effect of surface quality on mechanical performance.

Pillar Fabrication (Lithography Etching):
- Patterning: Direct UV laser writers (VPG 200, MLA 150) for large pillars (D > 2 µm) and high-resolution electron-beam (e-beam) writing for small pillars (D ≤ 1 µm).
- Reactive Ion Etching (RIE): Performed using SF₆ (etchant) and C₄F₈ (passivation).
  - Large pillars (D > 2 µm) used alternating Bosch cycles (etching/passivation) for deep etching.
  - Small pillars (D ≤ 2 µm) used simultaneous etching and passivation.
Surface Engineering (Cleaning Cycle):
- Fluorocarbon Removal: Standardized solution of ammonium hydroxide and hydrogen peroxide.
- Ionic Contamination Removal: Mixture of sulfuric acid and hydrogen peroxide.
- Damage Removal (Thermal Oxidation): A thermal oxide layer (2 µm thick for large pillars, 10 nm for small pillars) was grown in a wet atmospheric furnace. This step consumed the damaged surface Si.
- Final Surface Polish: The grown oxide layer was removed by immersion in an HF bath, resulting in a near-pristine, damage-free Si surface.
FIB Comparison Fabrication:
- Pillars of identical geometry were milled using a Helios G3 Ga⁺ FIB (30 kV) on both (100) and (123) oriented wafers.
- Progressively smaller milling currents (down to 40 pA for final polishing) were used to minimize taper and damage, though a ~40 nm amorphous layer persisted.
Mechanical Testing:
- Microcompression: Performed in situ in a SEM (Vega 3) using a diamond flat punch tip.
- Conditions: Constant strain rate of 5 x 10^-4 s^-1, compression axis parallel to (100) orientation.
- Data Conversion: Load-displacement curves were converted to engineering stress-strain curves, correcting for frame and substrate compliance.
Microstructure Analysis:
- Lamella Preparation: FIB lamellae were prepared from deformed pillars, ensuring the lamella plane contained the (100) compression axis and the (110) slip direction. Final polishing used low currents (7 pA) to minimize FIB artifacts.
- Characterization: TEM and STEM (Talos F200X, 200 kV) were used for bright-field (BF), dark-field (DF), and high-resolution TEM (HRTEM) imaging to analyze dislocation types (full vs. partial) and stacking faults.

Commercial Applications

The ability to achieve high strength and high elastic strain limits in micron-scale Si structures using standard semiconductor fabrication techniques opens several critical engineering pathways:

MEMS and Microsystems: Fabrication of highly robust structural components (e.g., gyroscopes, accelerometers) that can withstand extreme shock loading and mechanical stress without catastrophic brittle failure.
Strain Engineering in Electronics: Utilizing the ultrahigh elastic strain limit (6-7.5%) to significantly modify the band structure of Si channels in metal-oxide-semiconductor field-effect transistors (MOSFETs), thereby enhancing carrier mobility and device performance.
High-Performance Micro-Devices: Creating functional devices where performance is directly linked to the ability to sustain high elastic strains, such as high-frequency resonators or micro-actuators.
Advanced Nanofabrication: Establishing a validated surface engineering protocol (lithography + cleaning) for producing defect-scarce, high-quality Si building blocks, replacing damage-prone FIB milling for critical micro- and nanoscale structures.
Fundamental Materials Research: Providing a reliable method to study intrinsic size effects and dislocation dynamics in diamond-cubic semiconductors under high stress conditions at ambient temperature.

View Original Abstract

Abstract As the backbone material of the information age, silicon is extensively used as a functional semiconductor and structural material in microelectronics and microsystems. At ambient temperature, the brittleness of Si limits its mechanical application in devices. Here, we demonstrate that Si processed by modern lithography procedures exhibits an ultrahigh elastic strain limit, near ideal strength (shear strength ~4 GPa) and plastic deformation at the micron-scale, one order of magnitude larger than samples made using focused ion beams, due to superior surface quality. This extended elastic regime enables enhanced functional properties by allowing higher elastic strains to modify the band structure. Further, the micron-scale plasticity of Si allows the investigation of the intrinsic size effects and dislocation behavior in diamond-structured materials. This reveals a transition in deformation mechanisms from full to partial dislocations upon increasing specimen size at ambient temperature. This study demonstrates a surface engineering pathway for fabrication of more robust Si-based structures.

Tech Support

Original Source

DOI: https://doi.org/10.1038/s41467-020-16384-5