Boosting the MOSFETs Matching by Using Diamond Layout Style
At a Glance
Section titled âAt a Glanceâ| Metadata | Details |
|---|---|
| Publication Date | 2020-12-28 |
| Journal | Journal of Integrated Circuits and Systems |
| Authors | Vinicius Vono Peruzzi, Christian Renaux, Denis Flandre, Salvador Pinillos Gimenez |
| Institutions | UCLouvain, Centro UniversitĂĄrio FEI |
| Citations | 1 |
| Analysis | Full AI Review Included |
Executive Summary
Section titled âExecutive SummaryâThis study experimentally compares the device matching performance of standard Rectangular (CSnM) and innovative Diamond (DSnM) Silicon-On-Insulator (SOI) nMOSFETs for analog circuit applications.
- Core Value Proposition: The Diamond layout style significantly reduces device mismatch, offering a cost-effective alternative technique to boost the accuracy of analog SOI Complementary MOS (CMOS) Integrated Circuits (ICs).
- Optimal Geometry: DSnMs implemented with a hexagonal gate shape corresponding to an alpha ($\alpha$) angle of 90° demonstrated the best matching performance.
- Performance Achievement: The optimal DSnM configuration boosted device matching by an average of -45.8% (reduction in relative error, $\epsilon_r$) compared to equivalent CSnM counterparts.
- Reliability Metric: This optimal matching was achieved with a standard deviation of 20.1% across all measured electrical parameters and figures of merit.
- Physical Mechanism: The improved matching is attributed to two effects inherent to the Diamond geometry: the Longitudinal Corner Effect (LCE) and the Parallel Association of MOSFETs with Different Channel Lengths Effect (PAMDLE).
- Parameters Affected: The boost was observed across critical analog metrics, including saturation drain current (IDSsat), transconductance (gm), Early voltage (VEA), and on-state resistance (Ron).
Technical Specifications
Section titled âTechnical Specificationsâ| Parameter | Value | Unit | Context |
|---|---|---|---|
| Manufacturing Process | 1 | ”m | SOI CMOS Technology |
| Optimal Alpha Angle ($\alpha$) | 90 | ° | Hexagonal gate geometry for best matching |
| Average Matching Boost (Optimal $\alpha$) | -45.8 | % | Average reduction in relative error ($\epsilon_r$) across all parameters |
| Standard Deviation (Optimal $\alpha$) | 20.1 | % | Variability of matching improvement |
| Gate Oxide Thickness (tox) | 30 | nm | Fully Depleted SOI nMOSFETs |
| Silicon Film Thickness (tsi) | 80 | nm | Fully Depleted SOI nMOSFETs |
| Buried Oxide Thickness (tBox) | 390 | nm | Fully Depleted SOI nMOSFETs |
| Drain/Source Doping | 4 x 1020 | cm-3 | Doping concentration |
| Channel Doping | 6 x 1016 | cm-3 | Doping concentration |
| Typical Bias Condition (VDS) | 1 | V | Saturation/Moderate Inversion Regime |
| Typical Bias Condition (VGS) | 0.4 | V | Saturation/Moderate Inversion Regime |
| Total Devices Analyzed | 360 | Devices | Sample size across 9 Integrated Circuits (ICs) |
Key Methodologies
Section titled âKey MethodologiesâThe experimental comparative study involved fabricating and characterizing DSnM and CSnM devices using a commercial SOI CMOS process.
- Fabrication: Devices were manufactured using a 1 ”m SOI CMOS process provided by Université catholique de Louvain (UCL).
- Device Sample Preparation: A total sample of 360 transistors was analyzed, consisting of 20 pairs (DSnM and CSnM counterparts) per Integrated Circuit (IC), across 9 ICs.
- Equivalence Criteria: CSnM (rectangular) devices were designed to have the same channel width (W) and gate area (AG) as their DSnM (hexagonal) counterparts. The CSnM channel length (L) was set to the average of the smallest (b) and largest (B) DSnM channel lengths.
- Geometric Variation: Four different channel widths (12 ”m, 24 ”m, 30 ”m, 180 ”m) were tested across five different alpha ($\alpha$) angles (36.9°, 53.1°, 90°, 126.9°, and 143.1°).
- Electrical Characterization: Measurements were performed using a Keithley 4200 semiconductor characterization system.
- Matching Quantification: Device matching was quantified by calculating the relative error ($\epsilon_r$) in percentage, comparing the standard deviation and average values of DSnMs versus CSnMs for key parameters (IDSsat, gm, VEA, Ron).
- Normalization: Parameters were normalized by the Aspect Ratio (AR) or Channel Length (L) to isolate the effects of LCE and PAMDLE.
Commercial Applications
Section titled âCommercial ApplicationsâThe Diamond layout style offers significant advantages for applications requiring high-precision analog performance and low mismatch, particularly in SOI technology.
- High-Precision Analog CMOS ICs: Direct application in circuits where device matching is paramount for performance stability and accuracy.
- Operational Transconductance Amplifiers (OTAs): Essential for improving the performance of differential input stages, which rely heavily on matched transistors.
- Low-Power/Fully Depleted SOI Circuits: The technique is directly applicable to fully depleted SOI MOSFETs, benefiting low-power and high-speed applications.
- Sensor Interface Electronics: Used in systems requiring high-accuracy signal conditioning and amplification where minimal offset voltage is critical.
- Voltage References and Current Mirrors: Improving the stability and accuracy of these fundamental analog building blocks by reducing statistical variability.
- RF/High-Frequency Circuits: Enhancing the matching of parameters like transconductance (gm) and unit voltage gain frequency (fT) for better high-frequency performance.
View Original Abstract
This manuscript presents an experimental comparative study between the Metal-Oxide-Semiconductor (MOS) Silicon-On-Insulator (SOI) Field Effect Transistors, n-type, (nMOSFETs) matching, which are implemented with the hexagonal gate shape (Diamond) and standard rectangular ones. The main analog parameters and figures of merit of 360 devices are investigated. The results establish that the Diamond SOI MOSFETs with α angles equal to 90o can boost in more than in average -45.8% with a standard deviation of 20.1% the devices matching in comparison to those found with the typical rectangular SOI MOSFETs, concerning the same gate area and bias conditions. Consequently, the Diamond layout style is an alternative technique to reduce the nMOSFETsâ mismatching, considering the analog SOI Complementary MOS (CMOS) integrated circuits (ICs) applications.