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6CCVD Research

SiGeSn Quantum Dots in HfO2 for Floating Gate Memory Capacitors

At a Glance

Section titled “At a Glance”
MetadataDetails
Publication Date2022-03-07
JournalCoatings
AuthorsCătălin Palade, A. Slav, Ovidiu Cojocaru, V. S. Teodorescu, T. Stoïca
InstitutionsUniversity of Bucharest, Academy of Romanian Scientists
Citations12
AnalysisFull AI Review Included

Executive Summary

Section titled “Executive Summary”

This research demonstrates the successful fabrication and characterization of SiGeSn Quantum Dots (QDs) embedded in HfO2 for high-performance, CMOS-compatible floating gate memory capacitors.

  • High Performance: The optimized structures achieved high frequency-independent memory windows of 3-4 V and stored electron densities up to 2 x 1013 electrons/cm2.
  • Low Thermal Budget: The presence of Sn in the SiGe intermediate layer successfully decreased the SiGe crystallization temperature to 520-530 °C RTA, significantly improving CMOS compatibility compared to pure Si or Ge NC formation.
  • Dual QD Formation: Optimal annealing (520-530 °C) resulted in two distinct types of crystalline SiGeSn QDs: low Sn content (2 at.%) QDs positioned inside the floating gate, and high Sn content (up to 12.5 at.%) QDs located at the floating gate/HfO2 interfaces.
  • Charge Storage Mechanism: Memory effects are controlled by SiGeSn-related trapping states and low-ordering clusters at lower RTA temperatures (325-450 °C), transitioning to crystalline SiGeSn QDs as the primary storage centers at 520-530 °C.
  • Fabrication Method: The 3-layer stack (Gate HfO2/SiGeSn-HfO2/Tunnel HfO2) was fabricated using magnetron sputtering followed by Rapid Thermal Annealing (RTA) for nanocrystallization.
  • Failure Mechanism: RTA temperatures of 600 °C or higher led to a pronounced decrease in memory window, attributed to enhanced Sn diffusion and segregation, potentially increasing the conductivity of the HfO2 layers.

Technical Specifications

Section titled “Technical Specifications”
ParameterValueUnitContext
Maximum Memory Window (ΔVFB)4.0VM1 structure, 530 °C RTA, 5 min
Maximum Stored Electron Density (n)2.0 x 1013electrons/cm2M1 structure, 530 °C RTA, 5 min
Optimal RTA Temperature Range520-530°CFor crystalline QD formation and maximum performance
SiGeSn QD Composition (Internal)~2.1at.% SnLow Sn content QDs inside floating gate
SiGeSn QD Composition (Interface)~12.5at.% SnHigh Sn content QDs at HfO2 interfaces
SiGeSn QD Diameter (Estimated)~5nmGe-rich QDs (HRTEM)
SiGeSn Crystallization StructureDiamondN/AObserved structure, favored by Sn presence
Ge-Ge Raman Shift (Peak 1)~300cm-1Low Sn content SiGeSn NCs
Ge-Ge Raman Shift (Peak 2)~290cm-1High Sn content SiGeSn NCs
Gate HfO2 Thickness (M1 Design)16-17nmControl oxide layer
Floating Gate Thickness (M1 Design)9-10nmIntermediate SiGeSn-HfO2 layer
Tunnel HfO2 Thickness (M1 Design)7-8nmTunnel oxide layer
HfO2 NC Size (Gate Oxide)10-12nmMonoclinic phase (HRTEM/XRD)
Si Substrate Resistivity7-14Ωcmp-Si (100)

Key Methodologies

Section titled “Key Methodologies”

The MOS capacitor structures were fabricated using a combination of magnetron sputtering and rapid thermal annealing (RTA).

  1. Substrate Preparation:
    • (100) p-Si substrates (7-14 Ωcm) were used, followed by standard cleaning procedures.
  2. Thin Film Deposition (Magnetron Sputtering):
    • Tunnel HfO2: Deposited first using an HfO2 target (45-55 W RF power). Thickness range: 4-8 nm.
    • Floating Gate (SiGeSn-HfO2): Co-deposited for the intermediate layer (7-12 nm).
      • Targets used: SiGe (25-35 W DC), Sn (3.5-10 W DC), and HfO2.
      • Designed composition: 10% Sn: 90% SiGe (vol.) and 80% SiGeSn: 20% HfO2 (vol.).
    • Gate HfO2 (Control Oxide): Deposited last using an HfO2 target. Thickness range: 16-21 nm.
  3. Nanostructuring (Rapid Thermal Annealing - RTA):
    • Annealing performed in N2 (6N purity) atmosphere.
    • Temperature range investigated: 325-600 °C.
    • Optimal RTA conditions for QD formation: 520-530 °C for 5-10 min.
  4. Electrode Deposition:
    • Top and bottom Al electrodes were deposited via thermal evaporation.
    • Top contacts utilized shadow masks (1 mm x 1 mm area).
  5. Characterization Techniques:
    • Structural/Morphological: Cross-section TEM (XTEM/HRTEM) for layer thickness, lattice fringes (d111), and QD size/location.
    • Crystalline Structure: X-ray Diffraction (XRD) for HfO2 monoclinic phase and SiGeSn (111) diamond peak identification.
    • Composition/Crystallinity: Raman Spectroscopy (325 nm UV laser excitation) for Ge-Ge mode analysis and Sn content estimation.
    • Electrical Performance: Capacitance-Voltage (C-V) hysteresis loops measured at 100, 500 kHz, and 1 MHz to determine memory window (ΔVFB) and stored charge density (n).

Commercial Applications

Section titled “Commercial Applications”

The demonstrated SiGeSn/HfO2 floating gate technology is highly relevant for next-generation micro/nanoelectronics due to its material compatibility and performance metrics.

  • High-Density Non-Volatile Memories (NVMs): Directly applicable as high-performance charge storage nodes in Flash memory architectures, offering high stored electron density (up to 2 x 1013 electrons/cm2).
  • CMOS Integration: The use of HfO2 (a high-k dielectric already standard in CMOS) and the reduced thermal budget (~530 °C RTA) due to Sn alloying facilitate easier integration into existing silicon manufacturing processes.
  • Photonic Flash Memories: The SiGeSn alloy exhibits high Short-Wave Infrared (SWIR) photosensitivity. This enables potential development of memory devices where the threshold voltage shift can be controlled optically, leading to faster access speeds and lower energy consumption.
  • Advanced Gate Dielectrics: HfO2 is a key material for post-Si electronic devices. This work validates its use not only as a gate oxide but also as a matrix for embedded Group IV QDs.
  • Integrated Ferroelectric Devices: The HfO2 matrix shows potential for nanoscale ferroelectricity, suggesting a pathway for developing integrated ferroelectric memory devices or devices leveraging both charge storage and ferroelectric effects.
View Original Abstract

Group IV quantum dots (QDs) in HfO2 are attractive for non-volatile memories (NVMs) due to complementary metal-oxide semiconductor (CMOS) compatibility. Besides the role of charge storage centers, SiGeSn QDs have the advantage of a low thermal budget for formation, because Sn presence decreases crystallization temperature, while Si ensures higher thermal stability. In this paper, we prepare MOS capacitors based on 3-layer stacks of gate HfO2/floating gate of SiGeSn QDs in HfO2/tunnel HfO2/p-Si obtained by magnetron sputtering deposition followed by rapid thermal annealing (RTA) for nanocrystallization. Crystalline structure, morphology, and composition studies by cross-section transmission electron microscopy and X-ray diffraction correlated with Raman spectroscopy and C-V measurements are carried out for understanding RTA temperature effects on charge storage behavior. 3-layer morphology and Sn content trends with RTA temperature are explained by the strongly temperature-dependent Sn segregation and diffusion processes. We show that the memory properties measured on Al/3-layer stack/p-Si/Al capacitors are controlled by SiGeSn-related trapping states (deep electronic levels) and low-ordering clusters for RTA at 325-450 °C, and by crystalline SiGeSn QDs for 520 and 530 °C RTA. Specific to the structures annealed at 520 and 530 °C is the formation of two kinds of crystalline SiGeSn QDs, i.e., QDs with low Sn content (2 at.%) that are positioned inside the floating gate, and QDs with high Sn content (up to 12.5 at.%) located at the interface of floating gate with adjacent HfO2 layers. The presence of Sn in the SiGe intermediate layer decreases the SiGe crystallization temperature and induces the easier crystallization of the diamond structure in comparison with 3-layer stacks with Ge-HfO2 intermediate layer. High frequency-independent memory windows of 3-4 V and stored electron densities of 1-2 × 1013 electrons/cm2 are achieved.

Tech Support

Section titled “Tech Support”

Original Source

Section titled “Original Source”

References

Section titled “References”
  1. 2020 - Semiconductor quantum dots for memories and neuromorphic computing systems [Crossref]
  2. 2018 - A review on Ge nanocrystals embedded in SiO2 and high-k dielectrics [Crossref]
  3. 2016 - Effect of hydrogen ion beam treatment on Si nanocrystal/SiO2 superlattice-based memory devices [Crossref]
  4. 2016 - Germanium nanoparticles grown at different deposition times for memory device applications [Crossref]
  5. 2012 - Fast programming metal-gate Si quantum dot nonvolatile memory using green nanosecond laser spike annealing [Crossref]
  6. 2011 - Carbon nanotube memory by the self-assembly of silicon nanocrystals as charge storage nodes [Crossref]
  7. 2019 - Self-assembled Sn nanocrystals as the floating gate of nonvolatile flash memory [Crossref]
  8. 2016 - Non-volatile memory devices based on Ge nanocrystals [Crossref]
  9. 2016 - Superior endurance performance of nonvolatile memory devices based on discrete storage in surface-nitrided Si nanocrystals [Crossref]
  10. 2015 - Multilayer Ge nanocrystals embedded within Al2O3 matrix for high performance floating gate memory devices [Crossref]

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