Skip to content
6CCVD Research

Single-Charge Tunneling in Codoped Silicon Nanodevices

At a Glance

Section titled “At a Glance”
MetadataDetails
Publication Date2023-06-22
JournalNanomaterials
AuthorsDaniel Moraru, Tsutomu Kaneko, Yuta Tamura, Taruna Teja Jupalli, Rohitkumar Shailendra Singh
InstitutionsAlexandru Ioan Cuza University, Shizuoka University
Citations8
AnalysisFull AI Review Included

Executive Summary

Section titled “Executive Summary”
  • Core Achievement: Demonstrated single-charge tunneling (SET) and band-to-band tunneling (BTBT) functionalities in highly codoped (Phosphorus donors and Boron acceptors) Silicon-on-Insulator (SOI) nanodevices.
  • Mechanism: Intentional codoping, even at high concentrations (up to 2.5 x 1020 cm-3), facilitates the formation of Dopant-Induced Quantum Dots (QDs) within the depletion layers (diodes) or nanoscale channels (transistors).
  • Diode Performance: Codoped p+n+ SOI diodes exhibited Esaki diode behavior, characterized by Negative Differential Conductance (NDC) with a peak-to-valley ratio of approximately 3, and BTBT transport mediated by discrete QD energy states.
  • Transistor Performance: Codoped SOI Field-Effect Transistors (FETs), designed as junctionless devices, showed clear, robust SET features (current peaks and Coulomb diamonds) at 8 K, suggesting multiple parallel QD paths in the channel.
  • Controllability: The substrate (back gate, Vsub) effectively modulated the potential landscape, revealing Coulomb diamonds in the diodes and confirming single-charge transport control in the highly compensated regions.
  • Fabrication: Devices were fabricated using CMOS-compatible techniques on SOI substrates, employing sequential two-step doping processes (pre-deposition and drive-in) and Electron Beam Lithography (EBL) for nanoscale patterning.

Technical Specifications

Section titled “Technical Specifications”
ParameterValueUnitContext
Measurement Temperature (T)8.0 ± 0.5KElectrical characterization environment.
Thermal Energy (kBT)0.7meVCorresponds to the measurement temperature.
P-Donor Concentration (ND)2.0 x 1020cm-3Codoped SOI-FET channel concentration.
B-Acceptor Concentration (NA)0.5 x 1020cm-3Codoped SOI-FET channel concentration.
Diode ND (P-doped region)2.5 x 1020cm-3Highly doped p+n+ diode leads.
Diode NA (B-doped region)1.5 x 1020cm-3Highly doped p+n+ diode leads.
Starting SOI Thickness50-70nmInitial top Si layer thickness.
Buried Oxide (BOX) Thickness150-200nmElectrical isolation layer thickness.
Gate Oxide Thickness (tox)10 ± 1nmThermally grown gate oxide for SOI-FETs.
FET Channel Length (L)~100 ± 20nmFinal dimensions of the nanoscale channel.
FET Channel Width (W)~30 ± 10nmFinal dimensions of the nanoscale channel.
NDC Peak-to-Valley Ratio (PTVR)~3-Observed in p+n+ SOI diodes (Esaki behavior).
Larger QD SET Period (ΔVG1)0.084 ± 0.005VInter-peak period in FET ID-VG characteristics.
Smaller QD SET Period (ΔVG2)0.038 ± 0.002VInter-peak period in FET ID-VG characteristics.
Estimated Gate Capacitance (CG1)2.3aFFitted parameter for the larger QD in the SET model.
Estimated Gate Capacitance (CG2)4.5aFFitted parameter for the smaller QD in the SET model.

Key Methodologies

Section titled “Key Methodologies”

The devices were fabricated using CMOS-compatible processes on Silicon-on-Insulator (SOI) substrates.

  1. SOI Preparation and Thinning:

    • Starting SOI layers (50-70 nm Si, 150-200 nm BOX) were thinned to the target thickness (tens of nm) using sacrificial oxidation (dry oxidation at 900-950 °C for 10-20 min) followed by diluted-HF etching.
    • An ultrathin protective SiO2 layer (~1.0 ± 0.5 nm) was thermally grown at 650 °C for 10 min prior to doping to minimize surface roughness.

  2. Codoping Process (Two-Step Sequential Doping):

    • P-Doping (Donors): Spin-coated P2O5 source (OCD59230) was used.
      • Pre-deposition: 600 °C for 30 min in N2 atmosphere.
      • Drive-in: Temperatures ranging from 860 °C to 1050 °C for various times (e.g., 975 °C for 10 min for diodes; 860 °C for 20 min for FETs).
    • B-Doping (Acceptors): Spin-coated B2O3 source (PBF6M-10) was used.
      • Pre-deposition: 600 °C for 30 min in O2 atmosphere (to burn off polymer solvent).
      • Drive-in: Temperatures ranging from 925 °C to 1050 °C for various times (e.g., 925 °C for 3 min for diodes; 960 °C for 5 min for FETs).
    • Masking: SiO2 masks (10-30 nm) and Si3N4 masks (10-20 nm) were used for selective doping in pn diode fabrication.

  3. Nano-Patterning and Metallization:

    • Patterns were defined using high-resolution Electron Beam Lithography (EBL) with low current exposure.
    • Unwanted Si film was removed using Reactive Ion Etching (RIE) to maintain abrupt side walls and minimize Line Edge Roughness (LER).
    • Gate oxide (for FETs) was formed by dry oxidation.
    • Al electrodes (200-300 nm thick) were deposited via vacuum evaporation using a two-step lift-off process.

  4. Characterization:

    • Resistivity measurements were performed using a four-point probe technique.
    • Electrical characterization (I-V, stability diagrams) was conducted in a vacuum chamber at low temperatures (T ≈ 8.5 K) using a semiconductor precision parameter analyzer.

Commercial Applications

Section titled “Commercial Applications”

The research focuses on fundamental physics in nanoscale silicon, providing a platform for future device architectures:

  • Quantum Computing and Information: Codoped silicon layers offer a scalable, CMOS-compatible platform for creating Dopant-Induced Quantum Dots (QDs), which are candidates for solid-state quantum bits (qubits).
  • Cryogenic Memory and Logic: The robust Single-Electron Tunneling (SET) features observed in the codoped FETs are essential for developing ultra-low-power, high-density memory and logic circuits designed for operation in the cryogenic environment (e.g., interfacing with quantum processors).
  • High-Speed Nanoelectronics: The observation of Negative Differential Conductance (NDC) in the p+n+ diodes (Esaki behavior) is relevant for high-frequency oscillators and mixers, potentially enabling extreme downscaling of these components.
  • Advanced Sensor Technology: SET devices are highly sensitive to local charge fluctuations, making them suitable for ultra-sensitive charge and displacement sensors at the nanoscale.
  • Fundamental Physics Exploration: Codoped SOI provides a controlled environment to study the interplay between donor and acceptor impurities at the atomic level, crucial for optimizing doping profiles in sub-10 nm transistors.
View Original Abstract

Silicon (Si) nano-electronics is advancing towards the end of the Moore’s Law, as gate lengths of just a few nanometers have been already reported in state-of-the-art transistors. In the nanostructures that act as channels in transistors or depletion layers in pn diodes, the role of dopants becomes critical, since the transport properties depend on a small number of dopants and/or on their random distribution. Here, we present the possibility of single-charge tunneling in codoped Si nanodevices formed in silicon-on-insulator films, in which both phosphorus (P) donors and boron (B) acceptors are introduced intentionally. For highly doped pn diodes, we report band-to-band tunneling (BTBT) via energy states in the depletion layer. These energy states can be ascribed to quantum dots (QDs) formed by the random distribution of donors and acceptors in such a depletion layer. For nanoscale silicon-on-insulator field-effect transistors (SOI-FETs) doped heavily with P-donors and also counter-doped with B-acceptors, we report current peaks and Coulomb diamonds. These features are ascribed to single-electron tunneling (SET) via QDs in the codoped nanoscale channels. These reports provide new insights for utilizing codoped silicon nanostructures for fundamental applications, in which the interplay between donors and acceptors can enhance the functionalities of the devices.

Tech Support

Section titled “Tech Support”

Original Source

Section titled “Original Source”

References

Section titled “References”
  1. 1949 - Electrical properties of pure silicon and silicon alloys containing boron and phosphorus [Crossref]
  2. 1965 - Cramming more components onto integrated circuits
  3. 2005 - The end of CMOS scaling: Toward the introduction of new materials and structural changes to improve MOSFET performance [Crossref]
  4. 2005 - Enhancing semiconductor device performance using ordered dopant arrays [Crossref]
  5. 2010 - Nanowire transistors without junctions [Crossref]
  6. 2006 - Transport spectroscopy of a single dopant in a gated silicon nanowire [Crossref]
  7. 2008 - Gate-induced quantum-confinement transition of a single dopant atom in a silicon FinFET [Crossref]
  8. 2010 - Single-electron transport through single dopants in a dopant-rich environment [Crossref]

Reads Similar to This

CVD-synthesis of detector quality diamond for radiation hardness detectors of ionizing radiation Extension of Spin Dephasing Time of Continuously Excited Ensemble Nitrogen Vacancy Centers by Double‐Quantum Ramsey Magnetometry with Spin Bath Driving Single-electron tunneling operation via a-few-donor quantum dots in SOI-FETs up to room temperature