Single-Electron Transistor Operation of a Physically Defined Silicon Quantum Dot Device Fabricated by Electron Beam Lithography Employing a Negative-Tone Resist
At a Glance
Section titled âAt a Glanceâ| Metadata | Details |
|---|---|
| Publication Date | 2023-06-01 |
| Journal | IEICE Transactions on Electronics |
| Authors | Shimpei Nishiyama, Kimihiko Kato, Yongxun Liu, Raisei Mizokuchi, Jun Yoneda |
| Institutions | Tokyo Institute of Technology, National Institute of Advanced Industrial Science and Technology |
| Analysis | Full AI Review Included |
Executive Summary
Section titled âExecutive Summaryâ- Core Innovation: Demonstration of a scalable fabrication process for physically defined Silicon Quantum Dots (QDs) utilizing Electron Beam (EB) lithography with a negative-tone resist (ma-N2401).
- Scalability & Compatibility: The use of a negative-tone resist improves compatibility with advanced CMOS processes, such as Shallow Trench Isolation (STI), facilitating the co-integration of qubits and classical peripheral control circuits.
- Process Refinement: A two-step thermal oxidation process was implemented, successfully reducing Line Edge Roughness (LER) and shrinking the QD diameter (from 46 nm to 40 nm), enhancing charging energy.
- Device Performance: Single-Electron Transistor (SET) operation was confirmed at 3.8 K through the observation of Coulomb diamonds, validating the quality of the nanoscale structures.
- Key Metrics: Charging energies ranged from 7.5 meV to 18.0 meV, and the side gate tunability (alpha factor) was measured between 0.017 and 0.058 eV/V, suitable for future gate-based RF reflectometry sensing.
- Nanoscale Resolution: The process achieved critical dimensions necessary for qubit integration, including lithographic isolation gaps of approximately 50 nm and constriction widths of 19 nm.
Technical Specifications
Section titled âTechnical Specificationsâ| Parameter | Value | Unit | Context |
|---|---|---|---|
| Measurement Temperature | 3.8 | K | Electrical characterization (SET operation) |
| SOI Layer Thickness | 40 | nm | Starting material thickness |
| Buried Oxide (BOX) Thickness | 145 | nm | Starting material thickness |
| Thermal Gate Oxide Thickness | 3 | nm | Formed during the 2nd oxidation step |
| CVD-SiO2 Thickness | 70 | nm | Deposited on thermal oxide |
| Polysilicon Top Gate Thickness | 100 | nm | Used for electron accumulation |
| EB Acceleration Voltage | 130 | kV | Lithography exposure condition |
| EB Base Dose | 416 | ”C/cm2 | Used for ma-N2401 negative resist |
| Estimated Effective QD Diameter (Device A) | 20-40 | nm | Calculated from total capacitance (C) |
| Estimated Effective QD Diameter (Device B) | 30-50 | nm | Calculated from total capacitance (C) |
| SEM Observed QD Diameter (Post-Oxidation) | 40 | nm | Physically defined structure |
| Constriction Width (Post-Oxidation) | 19 | nm | Tunneling barrier width |
| Charging Energy (Device A) | 15.0-18.0 | meV | Derived from Coulomb diamond size |
| Charging Energy (Device B) | 7.5-12.5 | meV | Derived from Coulomb diamond size |
| Total Capacitance (C, Device A) | 9-11 | aF | Total dot capacitance |
| Alpha Factor (α, Device A) | 0.017-0.018 | eV/V | Side gate tunability (lever arm) |
| Alpha Factor (α, Device B) | 0.020-0.058 | eV/V | Side gate tunability (lever arm) |
| Source/Drain Implantation Energy | 10 | keV | P+ ion implantation |
| Source/Drain Implantation Dose | 1.5 x 1015 | cm-2 | P+ ion implantation |
Key Methodologies
Section titled âKey MethodologiesâThe fabrication process leverages negative-tone EB lithography and a specialized two-step oxidation sequence on a Silicon-on-Insulator (SOI) wafer:
- Resist Coating and Exposure:
- SOI wafer cleaned (diluted HF).
- Negative-tone resist (ma-N2401) coated and baked (140 °C pre-bake).
- EB exposure (130 kV, 416 ”C/cm2) incorporating Proximity Effect Correction (PEC) for mid-range effects to ensure accurate nanoscale patterning.
- Pattern Transfer:
- Development using Tetramethylammonium Hydroxide (TMAH, 2.38%) for 1 minute.
- Silicon layer etched using Inductive-Coupled Plasma Reactive-Ion Etching (ICP-RIE) with a mixture of HBr, O2, and Ar.
- Resist removed via O2 ashing.
- Two-Step Thermal Oxidation (LER Reduction and Shrinking):
- 1st Oxidation (Sacrificial): 3 nm thermal oxidation at 850 °C to remove etching damage from the SOI surface.
- Sacrificial oxide removed using diluted HF.
- 2nd Oxidation (Gate Insulator): 3 nm thermal oxidation at 850 °C, further improving LER and shrinking the QD diameter and constriction width (to 19 nm).
- Gate and Doping:
- Gate insulator completed by depositing 70 nm of CVD-SiO2.
- 100 nm Polysilicon deposited and patterned via EB lithography to form the top gate.
- Source/Drain regions formed by P+ ion implantation (10 keV, 1.5 x 1015 cm-2), using the top gate as a self-aligned mask.
Commercial Applications
Section titled âCommercial ApplicationsâThe developed fabrication technology is highly relevant for the advancement of solid-state quantum computing and high-resolution semiconductor manufacturing:
- Quantum Computing Processors: Enables the high-density integration of physically defined silicon spin qubits, which are compatible with existing CMOS infrastructure, accelerating the path toward large-scale quantum processors.
- Cryogenic Electronics: Provides a robust fabrication platform for co-integrating qubit devices with classical peripheral control circuits (e.g., signal amplifiers and readout electronics) necessary for operation at cryogenic temperatures.
- Advanced Nanofabrication: The successful use of negative-tone EB resist (ma-N2401) combined with PEC offers a high-resolution, high-throughput alternative to costly Extreme Ultraviolet (EUV) lithography for early-stage prototyping and low-volume production of nanoscale devices.
- Quantum Sensing: The demonstrated SET operation and competitive alpha factors support the development of highly sensitive charge sensors required for fast, gate-based RF reflectometry readout of qubit states.
- High-Density Memory and Transistors: The ability to precisely control nanoscale dimensions (down to 19 nm constriction width) and reduce LER is applicable to next-generation classical transistors and high-density non-volatile memory architectures.
View Original Abstract
We have proposed and demonstrated a device fabrication process of physically defined quantum dots utilizing electron beam lithography employing a negative-tone resist toward high-density integration of silicon quantum bits (qubits). The electrical characterization at 3.8K exhibited so-called Coulomb diamonds, which indicates successful device operation as single-electron transistors. The proposed device fabrication process will be useful due to its high compatibility with the large-scale integration process.