Investigating Surface Morphology and Subsurface Damage Evolution in Nanoscratching of Single-Crystal 4H-SiC

At a Glance

Metadata	Details
Publication Date	2025-08-14
Journal	Micromachines
Authors	Jianpu Xi, Xinxing Ban, Zhen Hui, Wenlan Ba, Lijuan Deng
Institutions	Zhengzhou Institute of Machinery, Henan University of Technology
Analysis	Full AI Review Included

Executive Summary

This study systematically investigated the evolution of surface morphology and subsurface damage (SSD) in single-crystal 4H-SiC during variable-load nanoscratching, providing critical guidance for precision machining optimization.

Material Removal Regimes Defined: Three distinct regimes were identified based on applied normal load: purely ductile (Load < 14.5 mN), brittle-to-ductile transition (14.5-59.3 mN), and brittle removal (Load > 59.3 mN).
Surface Smoothness is Misleading: Substantial SSD, including deep median cracks (>4 µm) and dislocation clusters (up to ~1.2 µm deep), was observed even within the transition zone where the surface appeared macroscopically smooth and defect-free.
Amorphous Layer Role: A thin amorphous layer formed at the indenter-substrate interface. This layer suppressed immediate surface defects but acted as a stress concentrator, promoting the nucleation and propagation of deep subsurface cracks.
Crack Propagation Mechanism: Cracks consistently initiated at slip line intersections and propagated along slip paths. The deflection direction was non-uniform (e.g., rightward vs. leftward), indicating sensitivity to local stress states rather than fixed crystallographic orientation.
Engineering Mandate: To achieve optimal machining quality and ensure high reliability for semiconductor applications, material removal processes must operate strictly within the purely ductile regime (Load < 14.5 mN) to eliminate latent SSD.

Technical Specifications

Parameter	Value	Unit	Context
Substrate Material	Single-crystal 4H-SiC	N-type	Polished wafer, 0.35 mm thickness
Initial Surface Roughness (Ra)	0.2	nm	Ultra-smooth starting condition
Indenter Type	Diamond Berkovich	Tip Radius: 20 nm	Edge-forward orientation
Scratching Plane	(0001) Si-face	Crystal Orientation: [11-20]	Test surface and direction
Applied Load Range	0 to 100	mN	Linearly increasing ramp loading
Scratching Speed	10	µm/s	Constant speed
Ductile Removal Threshold (Load)	< 14.5	mN	Corresponds to scratch depth < 113.7 nm
Brittle-to-Ductile Transition Range (Load)	14.5 to 59.3	mN	Transition zone
Brittle Removal Threshold (Load)	> 59.3	mN	Corresponds to scratch depth > 278.1 nm
Maximum Median Crack Length Observed	> 5	µm	Cross-section III (Load 47.7 mN)
Maximum SSD Layer Depth Observed	~4.4	µm	Cross-section I (Load 22.63 mN)
Maximum Dislocation Cluster Depth	~1.2	µm	Cross-section III (Load 47.7 mN)
TEM Lamella Size	5 x 5 x 60	µm x µm x nm	Prepared via FIB lift-out

Key Methodologies

The study utilized a multi-scale approach combining controlled mechanical testing with advanced structural characterization:

Nanoscratching Experimentation:
- A KLA Instruments G200X nanoindenter was used to perform variable-load scratching (0-100 mN) on the 4H-SiC (0001) Si-face using a 20 nm radius diamond Berkovich tip.
- Three replicate scratches were generated to ensure repeatability, and the central scratch was selected for detailed analysis.
Surface Morphology Analysis:
- Scanning Electron Microscopy (SEM) (ZEISS Gemini 300) was used to characterize the surface features, debris morphology (fine chips vs. blocky chunks), and defect initiation points across the 200 µm scratch length.
Subsurface Sample Preparation (FIB):
- Focused Ion Beam (FIB) milling was employed to prepare three cross-sectional lamellae (Slice I, II, and III) perpendicular to the scratch direction.
- Slices were strategically located at 45 µm, 70 µm, and 95 µm from the scratch start, corresponding to loads of 22.63 mN, 35.18 mN, and 47.73 mN, respectively (all within the BDT zone).
Subsurface Damage Characterization (TEM):
- Transmission Electron Microscopy (TEM) was used for high-magnification analysis of the subsurface structure.
- TEM identified and quantified the depth of the amorphous layer, the length and path of median cracks, the density and depth of dislocation clusters, and localized phase transformations (crystalline, nanocrystalline, amorphous zones).

Commercial Applications

The findings are directly applicable to optimizing manufacturing processes for high-performance SiC devices where surface and subsurface integrity are paramount.

High-Power Electronics (MOSFETs/Diodes): SiC substrates are essential for third-generation power devices. Eliminating SSD is critical, as defects degrade breakdown voltage and carrier mobility, limiting device performance and lifespan.
Chemical Mechanical Polishing (CMP) Optimization: The identification of the strict ductile regime (Load < 14.5 mN) provides a quantitative target for CMP and fixed abrasive lapping processes, ensuring material removal occurs without generating latent SSD.
Micro-Electro-Mechanical Systems (MEMS): Precision machining of SiC components for MEMS requires ultra-high integrity. Understanding the stress-driven nature of crack propagation allows for better tool design and process control to prevent structural failure.
Quality Control Metrology: The results emphasize that traditional surface roughness measurements (Ra) are insufficient. New quality control protocols must incorporate techniques (like non-destructive subsurface imaging) capable of detecting deep median cracks and dislocation clusters hidden beneath a smooth surface.

View Original Abstract

Single-crystal 4H silicon carbide (4H-SiC) is a key substrate material for third-generation semiconductor devices, where surface and subsurface integrity critically affect performance and reliability. This study systematically examined the evolution of surface morphology and subsurface damage (SSD) during nanoscratching of 4H-SiC under varying normal loads (0-100 mN) using a nanoindenter equipped with a diamond Berkovich tip. Scratch characteristics were assessed using scanning electron microscopy (SEM), while cross-sectional SSD was characterised via focused ion beam (FIB) slicing and transmission electron microscopy (TEM). The results revealed three distinct material removal regimes: ductile removal below 14.5 mN, a brittle-to-ductile transition between 14.5-59.3 mN, and brittle removal above 59.3 mN. Notably, substantial subsurface damage—including median cracks exceeding 4 μm and dislocation clusters—was observed even within the transition zone where the surface appeared smooth. A thin amorphous layer at the indenter-substrate interface suppressed immediate surface defects but promoted subsurface damage nucleation. Crack propagation followed slip lines or their intersections, demonstrating sensitivity to local stress states. These findings offer important insights into nanoscale damage mechanisms, which are essential for optimizing precision machining processes to minimise SSD in SiC substrates.

Tech Support

Original Source

DOI: https://doi.org/10.3390/mi16080935

References

2024 - Compound mechanical and chemical-mechanical polishing processing technique for single-crystal silicon carbide [Crossref]
2025 - Atomic-scale understanding of graphene oxide lubrication-assisted grinding of GaN crystals [Crossref]
2025 - Damage evolution mechanism and low-damage grinding technology of silicon carbide ceramics [Crossref]
2024 - Surface micro-morphology model involved in grinding of GaN crystals driven by strain-rate and abrasive coupling effects [Crossref]
2025 - Predictive models for the surface roughness and subsurface damage depth of semiconductor materials in precision grinding [Crossref]
2024 - Study of damage mechanism on single crystal 4H-SiC surface layer by picosecond laser modification (PLM) [Crossref]
2024 - Surface evolution and subsurface damage mechanism in fixed abrasive lapping of Silicon carbide [Crossref]
2025 - Damage assessment of 6H-SiC under repeated nano-scratching [Crossref]