Interlaced, Nanostructured Interface with Graphene Buffer Layer Reduces Thermal Boundary Resistance in Nano/Microelectronic Systems
At a Glance
Section titled āAt a Glanceā| Metadata | Details |
|---|---|
| Publication Date | 2016-11-23 |
| Journal | ACS Applied Materials & Interfaces |
| Authors | Lei Tao, Sreeprasad T. Sreenivasan, Rouzbeh Shahsavari |
| Institutions | Rice University |
| Citations | 42 |
Abstract
Section titled āAbstractāImproving heat transfer in hybrid nano/microelectronic systems is a challenge, mainly due to the high thermal boundary resistance (TBR) across the interface. Herein, we focus on gallium nitride (GaN)/diamond interface-as a model system with various high power, high temperature, and optoelectronic applications-and perform extensive reverse nonequilibrium molecular dynamics simulations, decoding the interplay between the pillar length, size, shape, hierarchy, density, arrangement, system size, and the interfacial heat transfer mechanisms to substantially reduce TBR in GaN-on-diamond devices. We found that changing the conventional planar interface to nanoengineered, interlaced architecture with optimal geometry results in >80% reduction in TBR. Moreover, introduction of conformal graphene buffer layer further reduces the TBR by ā¼33%. Our findings demonstrate that the enhanced generation of intermediate frequency phonons activates the dominant group velocities, resulting in reduced TBR. This work has important implications on experimental studies, opening up a new space for engineering hybrid nano/microelectronics.