Device SHEs in the Presence of Non-equilibrium Channel Heat Transport in SOI and SOD FinFETs with Technology Scaling

At a Glance

Metadata	Details
Publication Date	2020-11-26
Authors	Sankatali Venkateswarlu, Kaushik Nayak
Institutions	Indian Institute of Technology Hyderabad
Citations	1

Abstract

With scaling FinFETs in advanced logic technologies, fin thickness, source/drain (S/D) regions doping and lattice hot-spot temperature predominantly affect the fin channel thermal conductivity due to enhanced phonon boundary scattering and phonon-dopant impurity (mass and size) fluctuations and leads to more device SHE. In this paper, we investigated these effects on silicon-on-insulator (SOI) fin field effect transistor (FinFET) electro-thermal performance by TCAD analysis considering Boltzmann transport equation (BTE) for phonons with relaxation time approximation. Results showed that the channel kth is reduced for <tex>$\mathrm{W}{\text{Fin}} < 50\ \text{nm}$</tex>, doping <tex>$\mathrm{N} > 1\times 10^{19}\ \text{cm}-3$</tex> and it is further degraded due to increasing local hot-spot temperature. However, Silicon-on-diamond (SOD) technology improves the device ET performance due to increase in heat energy flux through diamond (higher kth) BOX layer towards the substrate. Impact of within-chip ambient temperature <tex>$(\mathrm{T}{\mathrm{A}})$</tex> on device logic performance reveals that the SOD FinFET exhibits lower hot-spot temperature compared to conventional SOI FinFET. It is also revealed that with SOD technology, FinFETs can be aggressively scale down to sub-10nm node with better lattice heat mitigation, which improves the FinFET logic performance.

Tech Support

Original Source

DOI: https://doi.org/10.1109/icee50728.2020.9777080

References

0 - 3d coupled electro-thermal FinFET simulations including the fin shape dependence of the thermal conductivity
2019 - Sentaurus device user guide, version P-2019.03
0 - A 14nm logic technology featuring 2 nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size