Influence of the DLC Passivation Conductivity on the Performance of Silicon High-Power Diodes Over an Extended Temperature Range

At a Glance

Metadata	Details
Publication Date	2021-01-01
Journal	IEEE Journal of the Electron Devices Society
Authors	Luigi Balestra, Susanna Reggiani, A. Gnudi, Elena Gnani, J. Dobrzynska
Institutions	University of Bologna, Czech Technical University in Prague
Citations	3
Analysis	Full AI Review Included

Executive Summary

This research investigates the thermal performance and leakage current mechanisms of 4.5 kV silicon high-power diodes passivated with doped Diamond-Like Carbon (DLC) layers across an extended temperature range (300 K to 413 K).

Core Problem Addressed: The leakage current (I_OFF) in DLC-passivated high-power diodes exhibits an unusual deviation from the standard Arrhenius law at lower temperatures, indicating that DLC conductivity significantly contributes to I_OFF.
Modeling Achievement: A comprehensive TCAD (Technology Computer-Aided Design) model was developed and validated to predict I_OFF and breakdown voltage (BV) behavior up to the maximum junction temperature (T_jmax = 413 K).
Key Mechanisms Modeled: The TCAD setup incorporates DLC bulk charge transport (using Gaussian Densities of States, G-DOSs, and Poole-Frenkel mobility), Si/DLC interface effects (thermionic emission), and ferroelectric polarization.
Validation: Rigorous calibration was achieved using J-V measurements from specially designed Metal-Insulator-Semiconductor (MIS) test structures with varying silicon substrate doping (n-type and p-type).
Doping Effects: The study compared Nitrogen-doped (NDLC) and Boron-doped (BDLC) DLC, showing that the doping type and concentration influence the Si/DLC interface depletion region width and, consequently, the leakage current and BV at room temperature.
Thermal Behavior: At high temperatures (413 K), the doping-induced electrostatic effects are compensated by thermal generation in the silicon, leading to similar depletion region widths regardless of the DLC doping type.

Technical Specifications

Parameter	Value	Unit	Context
Device Type	Fast-Recovery Diode	N/A	Large-area, circular, negative bevel
Nominal Blocking Voltage	4.5	kV	Device class under investigation
Extended Temperature Range (T_jmax)	300 to 413	K	Industrial operating range (27 °C to 140 °C)
Reverse Bias Measurement Voltage	4000	V	Used for I_OFF and BV analysis
Total DLC Thickness (NDLC)	98	nm	Measured thickness
Total DLC Thickness (BDLC)	140	nm	Measured thickness
DLC Energy Gap (E_g)	1.36	eV	Used in TCAD model
Hopping State Concentration (N_t) (NDLC)	2.43e21	cm^-3	Gaussian DOS parameter
Hopping State Concentration (N_t) (BDLC)	2e20	cm^-3	Gaussian DOS parameter
Poole-Frenkel Activation Energy (E_a) (NDLC)	0.16	eV	Fitted transport parameter
Poole-Frenkel Activation Energy (E_a) (BDLC)	0.23	eV	Fitted transport parameter
Relative Dielectric Constant (ε_r) (NDLC)	4	N/A	Used in TCAD model
Permanent Polarization (P_r) (NDLC)	3e-8	C/cm²	Ferroelectric model parameter
Si/DLC Conduction Band Barrier (ΔE_c)	0.12 to 0.3	eV	Analyzed range for interface effects

Key Methodologies

The investigation relied on a combination of experimental characterization of industrial diodes and specialized TCAD modeling calibrated against MIS test structures.

Device Characterization:
- Leakage current (I_OFF) was measured on 4.5 kV fast-recovery diodes under 4 kV reverse bias across temperatures ranging from 300 K to 413 K.
- Four different DLC passivation recipes were tested: Nitrogen-doped (NDLC) and Boron-doped (BDLC), each at two concentration levels (“dop1” and “dop2”).
MIS Structure Calibration:
- Special Metal-Insulator-Semiconductor (MIS) test structures, using the same DLC layers on both n-type and p-type silicon substrates, were fabricated.
- J-V characteristics of these MIS structures were measured from 300 K to 375 K to isolate and calibrate the DLC bulk and interface transport parameters.
TCAD Model Implementation (Synopsys Sentaurus Device):
- Geometry: 2D radial description was used for the circular power diode geometry.
- DLC Bulk Transport: Modeled using the drift-diffusion approach. Charge trapping was represented by two symmetric Gaussian Densities of States (G-DOSs) within the DLC energy gap (fixed at 1 eV separation).
- Temperature Dependence: The mobility of hopping carriers within the DLC was modeled using the Poole-Frenkel equation, incorporating an activation energy (E_a) fitted against the temperature dependence of the MIS J-V curves.
- Si/DLC Interface: Charge transport across the interface was modeled using the thermionic emission model for both electrons and holes. The metal work function was fixed to ensure Fermi-level pinning at the mid-gap, resulting in symmetric forward-bias J-V curves.
- Electrostatics: A ferroelectric model was included to account for polarization effects in the DLC, fitting the permanent polarization (P_r) against capacitance peaks observed in C-V measurements.

Commercial Applications

The validated TCAD model and the understanding of DLC conductivity are crucial for optimizing high-voltage semiconductor device design, particularly in applications requiring high reliability and extended temperature operation.

High-Power Conversion Systems: Essential for designing robust diodes used in high-voltage direct current (HVDC) transmission, railway traction, and large industrial motor drives.
IGBT and IGCT Modules: Directly applicable to improving the Safe Operating Area (SOA) and increasing the maximum allowed junction temperature (T_jmax) of high-power Insulated Gate Bipolar Transistors (IGBTs) and Gate Commutated Thyristors (IGCTs).
Reliability and Lifetime Extension: Enables accurate prediction of leakage current growth and breakdown stability over the device lifetime, crucial for long-term system reliability.
Advanced Junction Termination Design: Provides a predictive tool for optimizing the geometry and doping of semi-insulating passivation layers (like DLC) on beveled or planar junction terminations to maximize blocking voltage while minimizing active area consumption.
Semiconductor Manufacturing: The methodology allows for the selection and tuning of DLC deposition recipes (doping type and concentration) to achieve specific electrical properties required for optimal device performance.

View Original Abstract

The diamond-like carbon (DLC) is important for passivation of junction termination in high power devices due to its excellent electrical, mechanical, and thermal properties. While the role of conductivity and polarization of the DLC layer on the blocking capability of a p-n junction has been explained recently, the thermal behavior still needs to be addressed. For this purpose, the diode leakage current was measured on large area power diodes with negative bevel coated by the DLC in a typical industrial range between 300 and 413 K. An unusual deviation from the expected Arrhenius law was experimentally observed. A predictive TCAD model, which incorporates the effect of the DLC layer, has been developed to study the impact of the DLC layer parameters on diode thermal performance. Both the electrostatic features and charge transport mechanisms through and along the DLC/Silicon interface have been modeled over a wide range of temperatures. Different DLC/Silicon doping combinations have been analyzed to explain the main effects determining the temperature dependence of diode leakage current and breakdown voltage. A complete validation of the TCAD approach has been achieved.

Tech Support

Original Source

DOI: https://doi.org/10.1109/jeds.2021.3073232

References

2007 - Semiconductor component having a pn junction and a passivation layer applied on a surface