The Impact of LCE and PAMDLE Regarding Different CMOS ICs Nodes and High Temperatures

At a Glance

Metadata	Details
Publication Date	2021-01-01
Journal	IEEE Journal of the Electron Devices Society
Authors	Egon Henrique Salerno Galembeck, Christian Renaux, Jacobus W. Swart, Denis Flandre, Salvador Pinillos Gimenez
Institutions	UCLouvain, Universidade Estadual de Campinas (UNICAMP)
Citations	10
Analysis	Full AI Review Included

Executive Summary

Core Value Proposition: The Diamond Layout Style (DLS) for MOSFETs significantly boosts electrical performance compared to standard Rectangular MOSFETs (RLS) across different CMOS nodes and extreme temperatures (300K to 573K).
Mechanism Validation: The performance gains are confirmed to be driven by two intrinsic effects: the Longitudinal Corner Effect (LCE), which enhances the resultant longitudinal electric field (RLEF), and the PAMDLE effect, which reduces the effective channel length (L_eff).
Performance Gains: DLS devices (DM/DSM) showed average gains of 60% for saturation drain current (I_{DS_SAT}) and 51% for transconductance (g_m) compared to their RLS counterparts (RM/RSM).
Technological Independence: The LCE and PAMDLE effects remain active and provide similar percentage gains (difference less than 15%) regardless of the CMOS technology node used (180nm Bulk or 1µm SOI).
High-Temperature Stability: The performance improvements are maintained consistently throughout the entire tested temperature range (up to 573K), confirming DLS suitability for high-temperature electronics.
Analog Circuit Merit: DLS MOSFETs are capable of providing normalized g_m/(W/L) values approximately two times higher than RLS devices, making them superior for high-gain analog amplifiers and potentially doubling the transition frequency (f_T).

Technical Specifications

Parameter	Value	Unit	Context
Temperature Range Tested	300 to 573	K	Operating range for characterization.
CMOS Technology Nodes	180nm Bulk, 1µm SOI	N/A	Technologies used for device fabrication.
DM Channel Length (L)	0.54	µm	Bulk Diamond MOSFET.
DSM Channel Length (L)	8.0	µm	SOI Diamond MOSFET.
DM Effective Channel Length (L_eff) Reduction	23	%	Reduction relative to RM (due to PAMDLE).
DSM Effective Channel Length (L_eff) Reduction	20	%	Reduction relative to RSM (due to PAMDLE).
Average I_{DS_SAT} Gain (DLS vs. RLS)	60	%	Across all temperatures and nodes.
Average Transconductance (g_m) Gain (DLS vs. RLS)	51	%	Across all temperatures and nodes.
Maximum Intrinsic Gain (A_V) Gain (DLS vs. RLS)	63	%	Average gain of DM/DSM over RM/RSM.
DM Threshold Voltage (V_TH) @ 300K	0.50	V	Measured using second-derivative method.
DM Zero-Temperature Coefficient (ZTC) V_GS	0.75	V	Bulk devices (DM/RM) at V_DS = 1V.
DSM Zero-Temperature Coefficient (ZTC) V_GS	0.85	V	SOI devices (DSM/RSM) up to 473K.
DM Leakage Current (I_LEAK) Increase @ 523K	51	%	Higher I_LEAK due to larger junction area (A) and LCE effect.
g_m/I_DS Ratio Gain (Moderate Inversion)	9 to 15	%	DLS advantage across temperature and technology.

Key Methodologies

Device Implementation: N-type MOSFETs were fabricated using two distinct gate layout styles: Diamond Layout Style (DLS) and standard Rectangular Layout Style (RLS). Devices were implemented in both 180nm Bulk and 1µm Full-Depleted (FD) Silicon-On-Insulator (SOI) CMOS technologies.
Thermal Characterization: Electrical parameters were measured across a wide temperature range, starting from room temperature (300K) up to 573K, using controlled thermal stages.
Threshold Voltage (V_TH) Extraction: V_TH was determined using the second-derivative method, measured at a low drain-source voltage (V_DS = 50mV).
Analog Figure of Merit Analysis: Key analog performance indicators were extracted in the saturation regime, including saturation drain current (I_{DS_SAT}), transconductance (g_m), output conductance (g_D), and intrinsic gain (A_V = g_m/g_D).
Zero-Temperature Coefficient (ZTC) Identification: ZTC bias points (V_ZTC) were identified by observing the gate-source voltage (V_GS) where the drain current (I_DS) exhibited minimal variation with temperature, indicating mutual cancellation of mobility and V_TH temperature effects.
Leakage Current (I_LEAK) Analysis: I_LEAK was measured in OFF conditions to study the temperature dependence, distinguishing between the generation component (dominant below 423K, proportional to n_i) and the diffusion component (dominant above 423K, proportional to n_i²).

Commercial Applications

High-Temperature Automotive and Industrial Control: The verified stability and performance gains up to 573K (300°C) make DLS MOSFETs suitable for electronics operating near engines, power systems, or industrial processing equipment.
High-Gain Analog Amplifiers: The significant boost in transconductance (g_m) and intrinsic gain (A_V) directly supports the design of high-performance, high-gain analog integrated circuits (ICs).
Radio Frequency (RF) and Microwave Circuits: The potential to double the normalized transition frequency (f_T) suggests application in high-speed communication and radar systems requiring robust performance in harsh thermal environments.
Power Management and Conversion: Improved g_m/I_DS ratios indicate higher efficiency in converting DC power to AC frequency, beneficial for power management ICs and sensors.
CMOS Technology Migration: Since the LCE/PAMDLE benefits are consistent across both Bulk and SOI platforms, this layout technique can be readily integrated into existing and future CMOS manufacturing flows without requiring fundamental process changes.

View Original Abstract

This paper describes the influence of Longitudinal Corner Effect (LCE effect) and PArallel Connection of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) with Different Channel Lengths Effect (PAMDLE effect) of Diamond (hexagonal gate shape) MOSFET in different Complementary Metal-Oxide-Semiconductor (CMOS) Integrated Circuits (ICs) technologies (180nm-Bulk and 1μm- Silicon-On-Insulator, SOI) and in a wide range of high-temperatures (from 300K to 573K). The results have shown (average gains of Diamond MOSFET in relation to standard MOSFET: 60% for saturation drain current, 51% for transconductance, 10% for transconductance-over-drain current ratio etc.) that LCE and PAMDLE effects tend to be similar for CMOS ICs technological nodes used and the different high temperatures. Therefore, we can conclude, for the first time, that LCE and PAMDLE effects are kept active in different CMOS ICs technological nodes and when the Diamond MOSFET is exposed at high temperatures.

Tech Support

Original Source

DOI: https://doi.org/10.1109/jeds.2021.3071399

References

2018 - Temperature dependence and ZTC bias point evaluation of sub 20nm bulk multigate devices