Systematic high-level design of a fifth order Continuous-Time CRFF Delta Sigma ADC
At a Glance
Section titled âAt a Glanceâ| Metadata | Details |
|---|---|
| Publication Date | 2021-02-21 |
| Authors | M. Germain, F. Rarbi, O. Rossetto |
| Institutions | UniversitĂŠ Grenoble Alpes |
| Analysis | Full AI Review Included |
Executive Summary
Section titled âExecutive SummaryâThis paper details the systematic high-level design and simulation of a Continuous-Time Delta Sigma Analog-to-Digital Converter (CT ÎÎŁ ADC) optimized for high-speed energy measurement systems.
- Core Objective: Design a robust, high-level model for a fifth-order CT ÎÎŁ ADC targeting 10-bit Effective Number of Bits (ENOB) resolution.
- Target Application: Energy measurement systems used in particle identification, specifically utilizing diamond detectors, requiring wide bandwidth (40 MHz).
- Architecture Choice: A Cascaded Resonators Feedforward (CRFF) topology was selected for its ability to achieve high Signal-to-Quantization-Noise Ratio (SQNR) at a low OverSampling Ratio (OSR=8).
- Methodology: A Model-Based Design approach was implemented using MATLAB scripts integrated with SIMULINK graphical behavioral models (incorporating Schreierâs Toolbox).
- Synthesis Achievement: The ideal model achieved a simulated ENOB of 11.9 bits (73.5 dB SQNR), exceeding the 10-bit target specification.
- Robustness Analysis: Parametric Monte Carlo simulations (10,000 iterations) were performed to analyze the impact of component dispersion (R/C process variation) on loop coefficients.
- Key Finding: Under 20% process variation and 1% mismatch error, the mean SQNR dropped significantly to 51.7 dB, highlighting the critical sensitivity of the loop coefficients (a1, a2, b1, c1) to fabrication non-idealities.
Technical Specifications
Section titled âTechnical Specificationsâ| Parameter | Value | Unit | Context |
|---|---|---|---|
| Target ENOB Resolution | 10 | bits | Required for energy measurement systems |
| Simulated ENOB (Ideal) | 11.9 | bits | Achieved in behavioral simulation |
| Signal Bandwidth (BW) | 40 | MHz | Target input frequency range |
| Sampling Frequency (fs) | 640 | MHz | Determined by OSR |
| OverSampling Ratio (OSR) | 8 | - | Low ratio chosen for wideband design |
| Loop Filter Order (L) | 5 | - | Fifth-order modulator architecture |
| Quantizer Resolution (N) | 3 | bits | Modulator internal ADC resolution |
| Theoretical SQNR | 80 | dB | Calculated maximum performance |
| Simulated SQNR (Ideal) | 73.5 | dB | Achieved in behavioral simulation |
| Mean SQNR (Dispersion) | 51.7 | dB | Result of 10,000 iterations with Îp = 20%, δm = 1% |
| Integrator DC Gain | 40 | dB | Specified for all five Opamp-RC integrators |
| Integrator Saturation | 450 | mV | Maximum output swing limit for integrators |
| Linearity Target | <0.2 | % | Required specification |
Key Methodologies
Section titled âKey MethodologiesâThe design and analysis relied on a systematic, high-level modeling approach combining established tools with custom scripting:
- Model-Based Design (MBD): The CT ÎÎŁ modulator was implemented as a graphical behavioral model in SIMULINK, based on the general definition of the CRFF architecture.
- Synthesis Tool Integration: Schreierâs Toolbox [6] was used to synthesize the initial, ideal loop coefficients (ai, bi, ci, gi) required to meet the 40 MHz BW and 10-bit ENOB specifications.
- Custom Scripting: MATLAB scripts were developed and integrated to control the SIMULINK model, allowing for automated simulation runs and systematic analysis of non-idealities.
- Component Dispersion Modeling: The variation of loop coefficients (Xi) due to fabrication process was modeled using the equation: Xi = Xsi * (1 + Îpi + δmi).
- Îpi represents process variation error (tested up to 20%).
- δmi represents mismatch error (tested up to 1%).
- Parametric Monte Carlo Simulation: 10,000 iterations were run, varying each loop coefficient independently according to a normal Gaussian distribution within the defined error range (e.g., Îp = 20%, δm = 1%).
- Performance Extraction: For each iteration, the script injected the dispersed coefficients, ran the SIMULINK simulation with a 40 MHz sine wave input, and calculated the resulting SQNR and ENOB from the digital output spectrum.
- Critical Parameter Identification: Through iterative simulations, the coefficients a1, a2, b1, and c1 were identified as the most critical parameters, requiring the tightest design tolerance (e.g., reducing Îp to 10% and δm to 0.5%) to maintain acceptable SQNR.
Commercial Applications
Section titled âCommercial ApplicationsâThe systematic design methodology and the resulting high-performance CT ÎÎŁ ADC architecture are relevant to several demanding engineering fields:
- Particle Physics and Detection: Used specifically for energy measurement systems in new generation detectors (e.g., based on diamond), requiring fast, precise signal digitization from front-end electronics.
- High-Speed Data Acquisition (DAQ): Applicable in systems requiring wideband conversion (40 MHz BW) at high sampling rates (640 MHz) for scientific instrumentation and testing.
- Front-End Electronics (FEE) Design: Provides a robust, systematic method for designing complex analog control and signal processing blocks, reducing design time and effort during the schematic phase.
- CMOS Analog Integrated Circuits (IC): The methodology allows designers to estimate the impact of process variation (R/C time constant shifts) early in the design flow, ensuring manufacturability and yield for Opamp-RC integrator-based circuits.
- Telecommunications: Potential use in high-speed receivers or base stations where wide bandwidth and moderate resolution are required, and where low OSR is advantageous.
View Original Abstract
In this paper we present the development of a Systematic high level design model based on MATLAB scripts. It is integrated into a graphical behavioral model toolbox for the synthesis and simulation of a Continuous-Time Delta Sigma ADC. For this, we decided to use a Model-based design approach which it is adopted to address problems associated with designing complex control and signal processing systems such as the case of Continuous-Time Delta Sigma ADC. The goal of our study is the design of a 10 bit ENOB ADC for energy measurement systems used in particle identification through a new generation of detectors based on diamond. Results of the synthesis of a proposed fifth order Continuous-Time Delta Sigma ADC modulator for 10-bit ENOB ADC based on a Cascaded Resonators Feedforward architecture and simulations of the dispersion of its components (due to fabrication process) using the proposed tool are demonstrated and discussed.