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6CCVD Research

Optimizing a Robust Miller OTA Implemented with Diamond Layout Style for MOSFETs By Using iMTGSPICE

At a Glance

Section titled “At a Glance”
MetadataDetails
Publication Date2021-08-23
AuthorsJosĂ© Roberto Banin JĂșnior, Rodrigo Alves de Lima Moreto, Gabriel Augusto da Silva, Carlos Eduardo Thomaz, Salvador Pinillos Gimenez
InstitutionsCentro UniversitĂĄrio FEI
Citations2

Abstract

Section titled “Abstract”

This paper describes an innovative methodology to design and optimize robust analog Complementary Metal-Oxide-Semiconductor (CMOS) Integrated Circuits (ICs) with Diamond layout style (hexagonal gate shape) for Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), focusing on reducing their die areas and improving their electrical performances. The Miller CMOS Operational Transconductance Amplifier (OTA) is used to validate this design and optimization approach by using a computational tool, which integrates the human intelligence (expertise of the designer) and the artificial intelligence (use an evolutionary optimization algorithm to search robust potential solutions quickly and accurately). The 180 nm CMOS ICs technology node was considered in this work. The Longitudinal Corner Effect (LCE) and Parallel Connections of MOSFETs with different channel Lengths Effect (PAMDLE) present in the Diamond MOSFET structure are analytically modeled to be simulated in the SPICE. In addition, the iMTGSPICE computation tool was improved with a new feature to automatically convert Conventional MOSFETs (CMs) into Diamond MOSFETs (DMs). The main results show that the Miller CMOS OTA implemented with DMs (ɑ= 45°) can reduce up to 43% of their die area, practically without impairing the design specifications and robustness (Corner and Monte Carlo Analyses) in comparison to the one implemented with CM counterparts. Furthermore, these results were obtained quickly, i.e., approximately 4 hours to obtain five different robust potential solutions available to the designer.

Tech Support

Section titled “Tech Support”

Original Source

Section titled “Original Source”

References

Section titled “References”
  1. 2018 - Electrical performance of 130 nm PD-SOI MOSFET with diamond layout

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