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On the quantum performance evaluation of two distributed quantum architectures

MetadataDetails
Publication Date2021-10-13
JournalPerformance Evaluation
AuthorsGayane Vardoyan, Matthew Skrzypczyk, Stephanie Wehner
InstitutionsQuTech, Delft University of Technology
Citations8
AnalysisFull AI Review Included

This analysis compares two distributed quantum architectures—Single-Device (SD) and Double-Device (DD)—to quantify the impact of resource contention and waiting times on quantum state quality (fidelity).

  • Architectural Tradeoffs: The SD architecture (single device handling both computation and networking) is found to be more suitable for network-heavy applications (e.g., Quantum Key Distribution, QKD), while the DD architecture (separate devices for computation and networking) is superior for computation-heavy applications.
  • Fidelity Quantification: Novel analytical formulas were derived to link qubit waiting time distributions (modeled via Continuous-Time Markov Chains, CTMC) directly to the decay of Average Gate Fidelity (Favg) and Entanglement Fidelity (Fe) under standard quantum noise models.
  • DD Fidelity Advantage: When memory lifetimes (T1, T2) are identical, the DD architecture consistently yields a higher Favg for computational jobs because it allows parallel execution of networking and computation tasks.
  • SD Cost-Effectiveness: Sufficient conditions were established showing that an SD architecture with higher-quality memories (longer T1, T2) can outperform a DD architecture with poorer memories, offering a potentially more economical manufacturing path.
  • Platform Validation: The models were validated using the NetSquid simulator, specifically modeling the performance characteristics of Nitrogen-Vacancy (NV) centers in diamond, a leading platform for networked quantum nodes.
  • Noise Sensitivity: The post-move entanglement fidelity in the DD architecture is highly sensitive to the T2 memory lifetime of the components, highlighting the critical need for high-coherence storage.

The following parameters are extracted from the analysis and simulation context, primarily based on the Nitrogen-Vacancy (NV) center in diamond platform.

ParameterValueUnitContext
SD Moving Rate (”m(1))1667HzRate for local state transfer (swap operation) within the single device (600 ”s duration).
DD Moving Rate (”m(2))700HzExpected state transfer rate across the inter-device interface (teleportation based).
NV Bell-State Measurement Time1msMinimum duration for a key component of the DD state transfer sequence.
Qubit Memory Lifetime ConstraintT2 < 2T1N/ARequired relationship between T1 (damping) and T2 (dephasing) times for the composite noise model Ct.
QKD Fidelity Threshold0.81N/AMinimum entanglement fidelity required for secure Quantum Key Distribution.
Example High T1(1) (SD)10sMemory lifetime used in simulations demonstrating SD superiority over poorer DD memory.
Example Low T2(2) (DD)0.002sMemory lifetime used in simulations demonstrating DD inferiority to better SD memory.
Gate Depolarizing Probability (PG NV)0.02N/ADepolarizing noise applied to the Electron Spin (communication qubit) during initialization.
Electron-Carbon RCX PG0.005N/ADepolarizing noise applied during controlled-X gate operations between electron and carbon spins.

The performance evaluation relied on a hybrid analytical and simulation approach, focusing on queueing theory and quantum channel modeling.

  1. Architectural Queueing Model: Both SD and DD architectures were modeled as M/HYPO3/1 queueing systems using a Continuous-Time Markov Chain (CTMC).
    • Job Types: Requests were classified as Entanglement Generation, State Transfer (Moving), and Local Computation.
    • Processing Stages: Entanglement requests proceed through three stages: generation (rate ”e), waiting for move request arrival (rate λm), and moving execution (rate ”m).
  2. Waiting Time Distribution Derivation: The stationary distribution of the CTMC was solved analytically to obtain the probability density functions (fw(t)) for the waiting times of computational jobs in both SD and DD architectures.
  3. Fidelity-Time Correlation: General analytical formulas were derived to compute the average fidelity (Favg or Fe) by integrating the waiting time distribution fw(t) with the time-dependent fidelity decay function F(Nt, G).
    • Noise Models: Fidelity decay F(Nt, G) was calculated using standard quantum noise channels: Depolarizing (Dt), Dephasing (Pt), Amplitude Damping (At), and a Composite Channel (Ct).
  4. Simulation and Validation: The analytical results were validated using NetSquid, a discrete-event quantum network simulator.
    • Hardware Model: The simulation utilized a hardware-validated model of the NV center in diamond, including specific gate sequences for state transfer (e.g., the 6-gate sequence for NV-to-Carbon transfer).
  5. Priority Scheme (Simulation): In simulations where computational processing time (1/”c) was non-negligible, moving requests were assigned non-preemptive priority over computational jobs to reflect physical hardware constraints.

The architectural analysis provides critical design guidance for next-generation quantum hardware developers and network operators.

  • Quantum Networking Infrastructure: Design of quantum network nodes (routers and end nodes) using solid-state platforms (e.g., NV centers, Ion Traps) where resource contention between local computation and remote entanglement generation is a limiting factor.
  • Quantum Key Distribution (QKD): SD architecture is preferred for QKD applications, which are network-heavy and require high entanglement generation throughput, provided the local computation demands are low.
  • Distributed Quantum Computing: DD architecture is preferred for computation-heavy applications, such as secure delegated quantum computation in the cloud, where minimizing noise during long local processing periods is paramount.
  • Quantum Repeater Technology: Optimizing the architecture of repeater nodes, which must balance entanglement purification (local computation) with long-distance entanglement swapping (networking).
  • Qubit Memory Manufacturing: Establishing quantitative targets for T1 and T2 memory lifetimes required for specific architectural choices to meet application fidelity thresholds (e.g., determining if improving SD memory quality is more cost-effective than building a complex DD system).
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