Design Optimization of Three-Stacked Nanosheet FET From Self-Heating Effects Perspective
At a Glance
Section titled “At a Glance”| Metadata | Details |
|---|---|
| Publication Date | 2022-06-09 |
| Journal | IEEE Transactions on Device and Materials Reliability |
| Authors | Sunil Rathore, Rajeewa Kumar Jaisawal, P. N. Kondekar, Navjeet Bagga |
| Institutions | Indian Institute of Information Technology Design and Manufacturing Jabalpur |
| Citations | 56 |
Abstract
Section titled “Abstract”Self-heating effect (SHE) is a severe issue arising in the nanoscale field-effect transistors (FETs). It raises the device’s lattice temperature several degrees higher than the ambient temperature and degrades the driving current. The diamond-based dielectric material may be a promising candidate to mitigate the SHE due to its significantly larger thermal conductivity value ( <inline-formula xmlns:mml=“http://www.w3.org/1998/Math/MathML” xmlns:xlink=“http://www.w3.org/1999/xlink”> <tex-math notation=“LaTeX”>$\text{k}{\mathrm{ th}}= 2000$ </tex-math></inline-formula> W.m <sup xmlns:mml=“http://www.w3.org/1998/Math/MathML” xmlns:xlink=“http://www.w3.org/1999/xlink”>−1</sup> .K <sup xmlns:mml=“http://www.w3.org/1998/Math/MathML” xmlns:xlink=“http://www.w3.org/1999/xlink”>−1</sup> ) than SiO <sub xmlns:mml=“http://www.w3.org/1998/Math/MathML” xmlns:xlink=“http://www.w3.org/1999/xlink”>2</sub> ( <inline-formula xmlns:mml=“http://www.w3.org/1998/Math/MathML” xmlns:xlink=“http://www.w3.org/1999/xlink”> <tex-math notation=“LaTeX”>$\text{k}{\mathrm{ th}}= 1.4$ </tex-math></inline-formula> W.m <sup xmlns:mml=“http://www.w3.org/1998/Math/MathML” xmlns:xlink=“http://www.w3.org/1999/xlink”>−1</sup> .K <sup xmlns:mml=“http://www.w3.org/1998/Math/MathML” xmlns:xlink=“http://www.w3.org/1999/xlink”>−1</sup> ). In this paper, we have investigated the potential of crystalline diamond to mitigate the SHE-induced degradation in a partially depleted silicon-on-diamond Nanosheet FET (PDSOD NSFET). The results are compared with the partially depleted silicon-on-insulator (PDSOI) NSFET. Using extensive TCAD simulations, we investigated the impact of varying the ambient temperature and nanosheet thickness on the performance metrics of PDSOD and PDSOI NSFET. Thus, our analysis reveals that PDSOD NSFET is a viable alternative to alleviate the SHE-induced thermal degradation for the same footprint area of SiO <sub xmlns:mml=“http://www.w3.org/1998/Math/MathML” xmlns:xlink=“http://www.w3.org/1999/xlink”>2</sub> used in PDSOI NSFET.