Second Generation of Layout Styles to Further Boosting the Electrical Performance and Reducing the Die Area of Analog MOSFETs
At a Glance
Section titled âAt a Glanceâ| Metadata | Details |
|---|---|
| Publication Date | 2022-09-17 |
| Journal | Journal of Integrated Circuits and Systems |
| Authors | Gabriel Augusto DaSilva, Salvador Pinillos Gimenez |
| Institutions | Centro UniversitĂĄrio FEI |
| Citations | 4 |
| Analysis | Full AI Review Included |
Executive Summary
Section titled âExecutive SummaryâThe research introduces the Half-Diamond MOSFET (HDM) layout style, the first element of the Second Generation of innovative layouts, designed to significantly enhance the electrical performance of analog MOSFETs.
- Core Value Proposition: HDM layouts further reduce the effective channel length (Leff) and total die area compared to first-generation Diamond (DM) layouts, while preserving key performance-boosting effects (LCE, PAMDLE, DEPAMBBRE).
- Fabrication Context: Devices were fabricated using a standard 180 nm Bulk CMOS ICs technology node.
- Performance Boost (IDSsat): HDM achieved a 17.2% higher normalized saturation drain current (IDSsat/(W/Lgeo)) compared to the same-area Conventional MOSFET (CM1).
- Analog Gain Improvement: The low-frequency open-loop voltage gain (Av0) of the HDM was 3.5% higher than the CM1 counterpart.
- Speed and Transconductance: HDM demonstrated a 22.2% increase in both maximum normalized transconductance (gmmax/(W/Lgeo)) and normalized unit voltage gain frequency (fT/(W/Lgeo)) over CM1.
- Area Efficiency: The HDM Leff was approximately 15.2% smaller than the CM1 Leff, enabling greater density for analog and mixed-signal ICs.
- Resistance Reduction: Normalized on-state resistance (RON.(Lgeo/W)) was reduced by 32.4% compared to CM1.
Technical Specifications
Section titled âTechnical Specificationsâ| Parameter | Value | Unit | Context |
|---|---|---|---|
| Technology Node | 180 | nm | Bulk CMOS ICs (TSMC/IMEC) |
| Gate Area (AG) | 0.46 | ”m2 | HDM, DM, CM1 comparison basis |
| HDM Geometric Channel Length (Lgeo) | 0.44 | ”m | Used for normalization |
| HDM Effective Channel Length (Leff) | 0.37 | ”m | Reduced by PAMDLE effect |
| Leff Reduction (vs. CM1) | 15.2 | % | HDM vs. Conventional (same AG) |
| Normalized Saturation Drain Current (IDSsat/(W/Lgeo)) | 10.7 | ”A | HDM @ VGT=100mV |
| IDSsat/(W/Lgeo) Gain (vs. CM1) | 17.2 | % | HDM performance boost |
| Normalized Max Transconductance (gmmax/(W/Lgeo)) | 81.2 | ”A/V | HDM @ VDS=800mV |
| Normalized Unit Voltage Gain Frequency (fT/(W/Lgeo)) | 12.9 | kHz | HDM @ VDS=800mV, Cload=1pF |
| Normalized On-State Resistance (RON.(Lgeo/W)) | 2.8 | kΩ | HDM @ VGT=100mV |
| RON Reduction (vs. CM1) | 32.4 | % | HDM performance boost |
| Low-Frequency Intrinsic Voltage Gain (Av0) | 46.2 | dB | HDM @ VDS=800mV |
| Threshold Voltage (VTH) | 0.460 | V | HDM |
Key Methodologies
Section titled âKey Methodologiesâ- Device Selection and Fabrication: Four MOSFET types (Half-Diamond HDM, Diamond DM, Conventional CM1, and minimum-length Conventional CM2) were fabricated using the 180 nm Bulk CMOS ICs process.
- Geometric Matching: HDM, DM, and CM1 were designed to maintain an identical gate area (AG = 0.46 ”m2) to ensure a fair comparison of layout efficiency and performance effects.
- Layout Strategy (HDM): The HDM structure utilized a hybrid gate geometry, combining a triangular Diamond section near the drain and a rectangular section near the source, specifically designed to minimize the B dimension and maximize Leff reduction.
- Performance Normalization: All measured electrical parameters (IDS, gm, fT) were normalized by the geometric aspect ratio (W/Lgeo) to properly account for the Parallel Connection of MOSFETs with Different Channel Lengths Effect (PAMDLE).
- Electrical Characterization: Devices were tested under identical bias conditions. Measurements included:
- IDS vs. VGT (Triode Region, VDS=100mV).
- IDS vs. VDS (Saturation Region, VGT=100mV).
- Figure of Merit Calculation: Analog figures of merit, including maximum transconductance (gmmax), unit voltage gain frequency (fT), and intrinsic voltage gain (Av0), were calculated from the experimental I-V curves to quantify the performance benefits derived from the LCE and PAMDLE effects.
Commercial Applications
Section titled âCommercial ApplicationsâThe significant improvements in speed (fT), gain (Av0), and current drive (IDSsat) combined with die area reduction make the Half-Diamond layout highly relevant for advanced integrated circuit design.
- High-Performance Analog ICs: Ideal for core analog blocks such as operational amplifiers, comparators, and filters, where high intrinsic voltage gain (Av0) and transconductance (gm) are essential for maximizing signal integrity and reducing power consumption.
- Radiofrequency (RF) Systems: The substantial boost in fT (22.2% over CM1) makes HDM suitable for high-frequency applications, including RF front-ends, low-noise amplifiers (LNAs), and high-speed data converters.
- Mobile and Portable Electronics: The ability to reduce Leff and overall die area while maintaining or improving performance directly addresses the critical size and power constraints of modern mobile devices and IoT sensors.
- Power Management ICs (PMICs): The 32.4% reduction in RON makes HDM beneficial for integrated switches and drivers within PMICs, improving efficiency and reducing resistive losses.
- Radiation-Tolerant Design: By preserving the DEPAMBBRE effect, the HDM layout maintains robustness against Total Ionizing Dose (TID) effects, making it applicable for space, defense, and high-energy physics instrumentation.
View Original Abstract
Previous studies have been showing that the first generation of layout styles composed by the Diamond (hexagonal), Octo (octagonal) and Ellipsoidal gate shapes for implementing of the planar and three-dimensional MOSFETs are is capable of boosting their analog and digital electrical performances and also by reducing used die areas, when we replace conventional Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs), that present rectangular gate shape, by those implemented by these innovative layout styles. In order to further boosting these features obtained by the use of first generation of layout styles, we are introducing one of elements of the second generation of layout styles for MOSFETs, intitled Half-Diamond. This new proposal is an evolution of Diamond layout style, in which it is able to preserve the Longitudinal Corner Effect (LCE), the Parallel Connection of MOSFETs with Different Channel Lengths Effect (PAMDLE) and the Deactivation of Parasitic MOSFETs in Birdâs Beaks Regions (DEMPAMBBRE) effects of the first generation and also of further reducing the dimensions of conventional MOSFETs (CM) in which the Diamond MOSFETs have gotten to do. Thus, this work performs an experimental comparative study between the electric performances of MOSFETs implemented with the Half-Diamond, Diamond and Conventional layout styles, regarding the analog Complementary MOS (CMOS) integrated circuits (ICs) applications, which their channel lengths are not usually designed with the minimum dimension (Lmin) allowed by the CMOS ICs manufacturing processes. The results obtained show that, for instance, the saturation drain current normalized by the aspect ratio and low-frequency open-loop voltage gain, in dB, of MOSFET implemented with the Half-Diamond layout style (HDM) are 17% and 3.5% higher, respectively, than those found in CM counterparts. Besides, by using Half-Diamond layout style, it is possible of further reducing the die areas of analog CM and consequently of the analog CMOS ICs applications, in comparison to those reached by the use of Diamond layout styles, regarding a 180 nm Bulk CMOS ICs technology node.