Bottom-Up Cu Filling of High-Aspect-Ratio through-Diamond vias for 3D Integration in Thermal Management

At a Glance

Metadata	Details
Publication Date	2023-01-22
Journal	Micromachines
Authors	Kechen Zhao, Jiwen Zhao, Xiaoyun Wei, Xiaoyu Guan, Chaojun Deng
Institutions	Harbin Institute of Technology, Huawei Technologies (China)
Citations	9
Analysis	Full AI Review Included

Executive Summary

This research demonstrates a novel fabrication process for high-aspect-ratio Through-Diamond Vias (TDV) filled with copper, specifically targeting advanced thermal management in 3D integrated packaging.

Core Value Proposition: TDV leverages the ultra-high thermal conductivity of diamond (≥2000 W/mK) to replace thermally limiting Through-Silicon Vias (TSV), effectively addressing severe heat dissipation issues in high-power, high-density 3D-ICs.
Key Achievement: Successful bottom-up Cu electroplating of TDV structures featuring a high aspect ratio of 10:1 and an average longitudinal diameter of approximately 20 µm.
Process Optimization: A synergistic Ar/O hybrid plasma treatment was implemented to significantly improve the wettability of the diamond and metallization surfaces, crucial for complete electrolyte penetration.
Filling Quality: Optimal bottom-up filling was achieved at a current density of 0.3 ASD, confirmed by 3D-CT scans showing minimal leakage and the absence of top-surface pinch-off defects.
Electrical Performance: The fabricated Cu-filled TDV exhibited low electrical resistance, with an average single-via DC resistance calculated at 47.5 mΩ.
Thermal Impact: Finite Element Method (FEM) simulations demonstrated that integrating TDV significantly suppresses hot spot temperatures in stacked chips, achieving up to a 20 °C reduction compared to equivalent TSV structures.

Technical Specifications

Parameter	Value	Unit	Context
Diamond Thermal Conductivity	≥2000	W/mK	Bulk material property
Diamond Chip Thickness	200 ± 20	µm	Polycrystalline substrate thickness
Via Aspect Ratio (AR)	10:1	Ratio	Target design specification
Average Via Diameter	~20	µm	Longitudinal average
Via Entrance Diameter	~27	µm	After laser processing
Via Exit Diameter	~16	µm	After laser processing
Via Pitch	55	µm	Center-to-center spacing
Laser Wavelength	355	nm	UV nanosecond laser processing
Laser Pulse Width	12	ns	Laser processing parameter
Optimal Current Density	0.3	ASD	Bottom-up Cu electroplating
Single-Via DC Resistance	47.5	mΩ	Calculated average resistance
Plasma Treatment Power	300	W	Ar/O hybrid activation
Plasma Treatment Duration	2	min	Surface activation time
Temporary Bonding Temperature	200	°C	Hot pressing temperature
Simulated TIR (Bonding)	0.5	mm² K/W	Thermal Interface Resistance
Hot Spot Temperature Reduction	~20	°C	Simulated TDV vs. TSV performance

Key Methodologies

TDV Structure Fabrication:
- Polycrystalline diamond chips (10 x 10 mm²) were used as the substrate.
- High-AR vias were drilled using a UV nanosecond laser processing system (355 nm wavelength, 12 ns pulse width, 40 kHz repetition rate).
Metallization and Temporary Bonding:
- A uniform Cr/Au conductive layer was deposited on both sides of the diamond via Physical Vapor Deposition (PVD).
- The TDV chip was temporarily bonded to Au-deposited quartz flakes via hot pressing (5 MPa, 200 °C, 10 min), using the back-side Au layer as both the conducting layer and bonding layer.
Surface Pretreatment and Prewetting:
- Synergistic Ar/O hybrid plasma treatment (300 W, 2 min) was applied to the TDV surface to improve wettability, reducing the contact angle from 61° (flat diamond) to 47° (TDV surface).
- Vacuum-assisted prewetting was employed to ensure complete electrolyte diffusion into the high-AR vias and prevent air bubble entrapment.
Bottom-Up Cu Electroplating:
- A standard acid copper sulfate electrolyte was used, containing specific concentrations of accelerator (bis(3-sulfopropyl) disulfide), inhibitor (polyethylene glycol), and leveler (polyethyleneimine alkyl salt).
- Direct-current (DC) electroplating was performed at an optimized current density of 0.3 ASD for 4-10 hours until the outer surface of the vias was completely closed.
Characterization and Analysis:
- Filling quality was verified using 2D and 3D Computerized Tomography (CT).
- Stress distribution near the Cu-filled vias was analyzed using Raman spectroscopy.
- Electrical performance (resistance) was measured using the Kelvin four-point probe (4PP) method on serpentine test structures.

Commercial Applications

High-Power Semiconductor Devices: Essential for thermal management in devices where power density leads to severe localized heating, such as high-frequency GaN (Gallium Nitride) and SiC (Silicon Carbide) electronics.
3D Integrated Circuits (3D-IC) Packaging: Enables the next generation of vertical stacking by providing low-resistance electrical interconnection combined with highly efficient vertical heat extraction.
Advanced Interposers: Development of diamond-based interposers that offer superior thermal routing compared to traditional silicon or glass interposers, boosting overall system reliability.
Micro-Electromechanical Systems (MEMS): Applications requiring substrates with high thermal stability, electrical insulation, and corrosion resistance.
High-Density Memory and Logic Chips: Addressing the thermal limitations imposed by increased integration levels in high-speed computing environments.

View Original Abstract

Three-dimensional integrated packaging with through-silicon vias (TSV) can meet the requirements of high-speed computation, high-density storage, low power consumption, and compactness. However, higher power density increases heat dissipation problems, such as severe internal heat storage and prominent local hot spots. Among bulk materials, diamond has the highest thermal conductivity (≥2000 W/mK), thereby prompting its application in high-power semiconductor devices for heat dissipation. In this paper, we report an innovative bottom-up Cu electroplating technique with a high-aspect-ratio (10:1) through-diamond vias (TDV). The TDV structure was fabricated by laser processing. The electrolyte wettability of the diamond and metallization surface was improved by Ar/O plasma treatment. Finally, a Cu-filled high-aspect-ratio TDV was realized based on the bottom-up Cu electroplating process at a current density of 0.3 ASD. The average single-via resistance was ≤50 mΩ, which demonstrates the promising application of the fabricated TDV in the thermal management of advanced packaging systems.

Tech Support

Original Source

DOI: https://doi.org/10.3390/mi14020290

References

2010 - Wafer-Level bonding/stacking technology for 3D integration [Crossref]
2019 - Highly Efficient GaN-Based High-Power Flip- Chip Light-Emitting Diodes [Crossref]
2015 - 21-layer 3D chip stacking based on Cu-Sn bump bonding [Crossref]
2022 - MOSFETs on (110) C-H Diamond: ALD Al2O3/Diamond Interface Analysis and High Performance Normally-OFF Operation Realization [Crossref]
2019 - Microsystems Using Three-Dimensional Integration and TSV Technologies: Fundamentals and Applications [Crossref]
2021 - Ultra-high-performance heat spreader based on a graphite architecture with three-dimensional thermal routing [Crossref]
2014 - Review and projections of integrated cooling systems for three-dimensional integrated circuits [Crossref]