Design, Fabrication and Evaluation of Diamond Tip Chips for Reverse Tip Sample Scanning Probe Microscope Applications
At a Glance
Section titled âAt a Glanceâ| Metadata | Details |
|---|---|
| Publication Date | 2024-02-27 |
| Journal | Korean Journal of Materials Research |
| Authors | Sugil Gim, Thomas Hantschel, Jin Hyeok Kim |
| Institutions | IMEC, Chonnam National University |
| Analysis | Full AI Review Included |
Executive Summary
Section titled âExecutive SummaryâThis research details the development and evaluation of a simplified, high-performance diamond tip chip for Reverse Tip Sample (RTS) Scanning Probe Microscopy (SPM), primarily targeting Scanning Spreading Resistance Microscopy (SSRM).
- Process Optimization: The complex, multi-step fabrication process was streamlined by reducing the number of required pattern masks from three to two, resulting in a robust 2D array tip structure.
- Time and Yield Improvement: The simplified design successfully reduced the total fabrication time by over 50%, completing the tip-chip in approximately one week compared to the previous two weeks, while minimizing tip damage due to mask misalignment.
- Enhanced Resolution: A sharpening process was incorporated, creating Hedgehog Full Diamond Tips (HFDTs), which achieved superior high-resolution SSRM images compared to unsharpened tips.
- Low-Force Operation: Sharpened tips enabled accurate SSRM measurements at a significantly lower set-point (0.3 V) compared to the typical 1 V required by conventional SSRM tips, implying reduced mechanical load on the sample.
- Performance Validation: The new RTS tip-chips were successfully used to perform high-resolution quantitative dopant profiling on complex semiconductor structures, including Si calibration samples, FinFET devices, and GaAs nanoridges.
- Core Value Proposition: Provides a high-throughput, reliable, and high-resolution platform for 3D electrical profiling essential for next-generation nanoelectronic device development.
Technical Specifications
Section titled âTechnical Specificationsâ| Parameter | Value | Unit | Context |
|---|---|---|---|
| Required Tip Hardness | 8 - 12 | GPa | Minimum hardness required for high-resolution SSRM. |
| Tip-Chip Array Structure | 2D | Array | New simplified design utilizing two pattern masks. |
| Fabrication Time Reduction | 50+ | % | Reduced from 2+ weeks to 1 week. |
| KOH Etching Pattern Size | 15 x 15 | ”m2 | Square pattern size for inverse pyramid mold creation. |
| Diamond Film Growth Thickness | ~800 | ”m | Thickness of diamond film grown via HFCVD. |
| Nickel Electroplating Thickness | ~5.5 | ”m | Thickness used to form the cantilever and membrane. |
| Optimal KOH Etching Time | 6 | hours | Required for complete tip release from the silicon mold. |
| Sharpening Yield (Single HFDT) | ~30 | % | Percentage of tips achieving a single, sharp apex after RIE. |
| SSRM Set-Point (Sharpened Tip) | 0.3 | V | Low-force set-point used for FinFET/GaAs measurements. |
| SSRM Set-Point (Typical Tip) | 1 | V | Standard set-point for conventional SSRM tips. |
| SSRM Bias Voltage (FinFET) | +500 | mV | Applied bias during FinFET SSRM imaging. |
| SSRM Bias Voltage (GaAs) | +1 | V | Applied bias during GaAs nanoridge SSRM imaging. |
Key Methodologies
Section titled âKey MethodologiesâThe fabrication process for the RTS diamond tip-chip involves optimized microfabrication steps focusing on mold creation, diamond growth, and tip release/sharpening:
- Wafer Preparation and Masking (Mask 1): A hard mask layer (SiO2) is deposited onto the silicon wafer and patterned using the first mask to define 15 ”m x 15 ”m square arrays.
- Pyramid Mold Creation: Anisotropic etching using Potassium Hydroxide (KOH) is performed for 6 hours to create precise inverse pyramid molds in the silicon substrate.
- Diamond Deposition: Boron-doped diamond is grown to a thickness of approximately 800 ”m across the wafer using Hot-Filament Chemical Vapor Deposition (HFCVD).
- Seed Layer Deposition: A metal stack consisting of Titanium-Tungsten (TiW) (adhesion), Copper (Cu) (Ni plating seed), and Titanium (Ti) (protection) is sputtered onto the diamond film.
- Nickel Structure Formation (Mask 2): The second pattern mask is applied, followed by electroplating of Nickel (Ni) to a thickness of approximately 5.5 ”m, forming the structural cantilever and membrane components.
- Tip Sharpening (HFDT): The diamond tips are sharpened using Reactive Ion Etching (RIE) with O2/SF6 plasma, converting the tips into Hedgehog FDT (HFDT) structures.
- Chip Release: The remaining silicon substrate is under-etched using a second KOH etching step to fully release the completed 2D array tip-chips.
- Performance Evaluation: SSRM measurements are conducted in RTS mode on Si calibration samples, FinFETs, and GaAs nanoridge structures to verify high-resolution doping profile accuracy and low-force operation (0.3 V set-point).
Commercial Applications
Section titled âCommercial ApplicationsâThis technology is critical for industries requiring high-resolution, high-throughput electrical characterization of advanced semiconductor materials and devices.
- Advanced Nanoelectronics Manufacturing: Essential for quality control, failure analysis, and process monitoring of next-generation logic devices, including FinFETs and Gate-All-Around (GAA) architectures, where sub-nm dopant profiling is necessary.
- Semiconductor Research and Development: Enables quantitative 3D dopant mapping in novel materials (e.g., SiGe, III-V compounds like GaAs) to optimize device performance and yield.
- High-Throughput Metrology Systems: The RTS design allows for rapid, automated tip replacement, making it ideal for industrial metrology tools that require continuous operation and minimal downtime for tip maintenance.
- Materials Characterization: Applicable to the mechanical and electrical characterization of ultra-hard, conductive films and structures, leveraging the high hardness (8-12 GPa) and conductivity of the diamond tips.
- Scalpel SSRM Applications: Supports advanced techniques like scalpel SSRM, which combines material removal with electrical measurement for continuous vertical profiling of device cross-sections.
View Original Abstract
Scanning probe microscopy (SPM) has become an indispensable tool in efforts to develop the next generation of nanoelectronic devices, given its achievable nanometer spatial resolution and highly versatile ability to measure a variety of properties. Recently a new scanning probe microscope was developed to overcome the tip degradation problem of the classic SPM. The main advantage of this new method, called Reverse tip sample (RTS) SPM, is that a single tip can be replaced by a chip containing hundreds to thousands of tips. Generally for use in RTS SPM, pyramid-shaped diamond tips are made by molding on a silicon substrate. Combining RTS SPM with Scanning spreading resistance microscopy (SSRM) using the diamond tip offers the potential to perform 3D profiling of semiconductor materials. However, damage frequently occurs to the completed tips because of the complex manufacturing process. In this work, we design, fabricate, and evaluate an RTS tip chip prototype to simplify the complex manufacturing process, prevent tip damage, and shorten manufacturing time.