| Metadata | Details |
|---|
| Publication Date | 2024-04-04 |
| Journal | Journal of Electrical Systems |
| Authors | Shruti Suman Ashok D. Vidhate |
| Institutions | Koneru Lakshmaiah Education Foundation |
| Analysis | Full AI Review Included |
- Hybrid Device Development: A compact analytical model for a Hybrid Single Electron Transistor-Field Effect Transistor (SET-FET) circuit was developed and validated using the SIMON Monte Carlo simulator.
- Room Temperature Operation: The SET component, utilizing silicon nanodots (quantum islands less than 5 nm) layered in a Si/SiO2/Si nanopillar structure, is designed for stable operation at room temperature (300°K).
- Performance Enhancement: The hybrid structure successfully mitigates the low drive current drawback of standalone SETs, achieving a current range of 1 ”A - 4 ”A and a maximum voltage gain of 3, while maintaining ultra-low supply voltage (100 ”V).
- Variability Mitigation: SET-FET circuits significantly reduce device variability in larger nanoscale array configurations (e.g., 5x5 arrays) compared to traditional NWFET or FinFET architectures.
- CMOS Compatibility: The design leverages CMOS-compatible process specifications, facilitating the integration of high-sensitivity, low-power SETs with robust, high-impedance FETs.
- Modeling Foundation: The model is based on the orthodox theory of single electron tunneling and master equation methods, accurately replicating Coulomb blockade and oscillation effects.
| Parameter | Value | Unit | Context |
|---|
| SET-FET Supply Voltage Range | 100 ”V - 100 mV | V | Operating range |
| SET-FET Current Range | 1 ”A - 4 ”A | A | Operating range |
| SET-FET Maximum Voltage Gain | 3 | Ratio | Amplification factor |
| SET-FET Operating Temperature | 300°K | K | Designed for room temperature |
| SET-FET Maximum Switching Speed | 12 GHz | Hz | Performance metric |
| SET-FET Power Dissipation | 225 mW | W | Performance metric |
| Required Quantum Island Size | less than 5 nm | nm | Necessary for 300°K Coulomb blockade |
| Gate Oxide Target Thickness | 36.5 nm | nm | FET Compatible SET specification |
| Channel Implantation Dose (BF3) | 1.7 X 1012 | at/cm2 | FET Compatible SET specification |
| Source/Drain Implantation Dose (P/Ar) | 4.2 X 1015 | at/cm2 | FET Compatible SET specification |
| Substrate Resistivity | 8 - 22 Ω cm | Ω cm | P type SOI wafers |
| SET Charging Energy (Ec) | 40 kBT | J | Required for dependable room temperature design |
| Output Current Insensitivity | up to 1 pF | F | Capacitance limit for unaffected output current |
| Input Gate Resistance (RG) | 100 MΩ | Ω | Equivalent circuit model parameter |
| Resistance Combination (RG parallel R2) | 75 MΩ | Ω | Equivalent circuit calculation |
- Analytical Modeling: A compact analytical model was developed based on the âorthodox theoryâ of single electron tunneling and the steady-state master equation approach, accounting for eleven island states.
- Circuit Simulation: The model was implemented and validated using the SIMON (Single-Electron Device and Circuit Simulator) Monte Carlo simulator, which uses the Masterâs Equation method.
- Hybrid Architecture Design: The SET component (a quantum tunneling device using Si nanodots in an oxide layer) was co-integrated with a standard Field Effect Transistor (FET) in a hybrid configuration.
- CMOS Process Compatibility: The design utilized FET-compatible process specifications, including P-type SOI wafers and a buried oxide layer acting as the field oxide.
- Fabrication Steps (Simulated): Key steps included Polysilicon deposition by LPCVD, Channel implantation using BF3 gas, Source/Drain implantation using Phosphorous and Argon, and Metal routing via Al-Cu sputtering.
- Performance Characterization: IV characteristics, Coulomb diamond plots (charge stability diagrams), and Coulomb blockade oscillations were analyzed by varying VDS, VGS, and VBS.
- Variability Study: Device variability was assessed across various nanoscale array configurations (1x1 up to 5x5) for NWFET, FinFET, and SET-FET architectures to quantify the hybrid deviceâs stability advantage.
- Ultra-Low Power Integrated Circuits (ICs): Ideal for battery-operated devices and IoT sensors where minimal power dissipation (225 mW) is critical.
- High-Density Nano-electronics: Supports the global semiconductor technology roadmap approaching sub-nanometer scale IC production.
- Advanced Logic and Memory: Applicable in designing logic and memory blocks requiring low power consumption and minimal latency.
- Heterogeneous 3D Integration: The robust modeling and CMOS compatibility enable integration into complex 3D stacked architectures.
- Multi-Valued Logic (MVL) Circuits: The SET-FET structure is suitable for implementing MVLs, potentially increasing data density per transistor.
- Variability-Tolerant Arrays: The demonstrated ability to significantly reduce variability in large arrays makes it suitable for high-yield, large-scale manufacturing integration of nanoscale devices.
View Original Abstract
Gordon Mooreâs âMooreâs Lawâ suggests chip functionality demand doubles every 1.5-2 years, with global semiconductor technology roadmap recommending sub-nanometer ranges for IC production in nano-electronics. The single electron transistor (SET) is a promising nano-scale device that can be co-integrated with CMOS technology to improve performance. The paper explores the tunnelling effect between nanoparticles in single electron transistors (SET), revealing coulomb blockade transactions and resistance increases with reduced bias. It focuses on single electron transistors and pre-terminal devices, discussing IV characteristics, coulomb diamond plots, and metallic quantum dots. This research also explores the hybrid SET-FET based model, focusing on developing a room temperature SET in CMOS comparable technology with a Field Effect Transistor (FET). Prediction models and exploratory studies guide the integration of SET-FET technology. SIMON is a comprehensive simulator designed for single-electron devices and circuits. The output current is not impacted by capacitances up to 1 pF, and FET size in the micron range are appropriate for SET signal amplification up to 4 ”A. This research explores the modelling of SET-FET technology in highlighting its ability to mitigate drawbacks in low drive current when combined with a FET. It also explores device variability mitigation in nanoscale array configurations, finding that SET-FET significantly reduces variability in larger arrays, despite the impact of capacitance and resistance.