Experimental Study on the Role of Bond Elasticity and Wafer Toughness in Back Grinding of Single-Crystal Wafers

At a Glance

Metadata	Details
Publication Date	2025-10-25
Journal	Materials
Authors	Joong-Cheul Yun, Dae‐Soon Lim
Institutions	Korea University
Analysis	Full AI Review Included

Executive Summary

This study establishes a quantitative framework for optimizing the back-grinding process of single-crystal semiconductor wafers by linking grinding wheel bond elasticity (Eb) and wafer fracture toughness (K_IC) to diamond protrusion height (h_p).

Predictive Model Validation: A log-linear empirical model was derived (R² = 0.9525) that accurately predicts diamond protrusion height (h_p) based on the wheel’s Eb and the wafer’s K_IC, providing a unified parameter set applicable across Si, GaP, Sapphire, and SiC.
SiC Optimization: An optimal bond elastic modulus of 122.07 GPa (BGW4) was identified for 4H-SiC, achieving a high Material Removal Rate (MRR >740 µm/h) and low surface roughness (Ra ≈ 0.633 µm) while eliminating observable Subsurface Damage (SSD) cracks.
Bond Stiffness Effect: Increasing Eb systematically increases h_p and reduces grinding load across all materials. This effect is most pronounced in high-toughness materials (SiC), where higher Eb is necessary to maintain sufficient diamond protrusion and shift material removal toward fracture-based separation.
Toughness and Debris: Wafer K_IC dictates debris size, which in turn influences bond wear. High-toughness wafers (SiC, Sapphire) generate smaller debris (1-7 µm), suppressing bond erosion and stabilizing h_p, while low-toughness wafers (Si, GaP) generate larger debris (9-15 µm).
Industrial Guidance: The findings offer practical guidelines: use higher Eb for harder, high-K_IC wafers (like SiC) to ensure adequate h_p, and use moderate Eb for brittle, low-K_IC wafers (like Si) to balance h_p and control edge chipping.

Technical Specifications

Parameter	Value	Unit	Context
BGW Elastic Modulus (Eb) Range	95.24 to 131.38	GPa	Tested range across BGW1 to BGW5
Optimal Eb for 4H-SiC	122.07	GPa	BGW4 condition, minimizing SSD
SiC Fracture Toughness (K_IC)	2.64 ± 0.019	MPa·m^0.5	Highest K_IC among tested wafers
Si Fracture Toughness (K_IC)	0.63 ± 0.024	MPa·m^0.5	Lowest K_IC among tested wafers
Diamond Size (Median)	51.2	µm	Fixed abrasive grain size (≈D54)
Diamond Content	12.5	vol%	Fixed concentration in BGWs
Optimal SiC MRR (Thickness Rate)	>740.1 (up to 794.94)	µm/h	Achieved with BGW4
Optimal SiC MRR (Volumetric Rate)	100 (up to 107)	mm³/min	Equivalent rate for 81.07 cm² wafer
Optimal SiC Grinding Load	45.92 to 49.67	N	Achieved with BGW4
Optimal SiC Surface Roughness (Ra)	0.627 to 0.638	µm	Achieved with BGW4
SiC SSD Crack Length (Optimal)	0	nm	Observed using BGW4 (Eb=122.07 GPa)
SiC SSD Crack Length (Worst Case)	1197	nm	Observed using BGW1 (Eb=95.24 GPa)
Debris Size Range (SiC)	1 to 5	µm	Finer particles due to high K_IC
Debris Size Range (Si)	9 to 15	µm	Larger particles due to low K_IC

Key Methodologies

The back-grinding process was systematically evaluated by controlling the grinding wheel bond elasticity (Eb) and testing wafers with varying fracture toughness (K_IC).

Wafer Selection and Preparation:
- Four single-crystal materials (Si, GaP, Sapphire, 4H-SiC) were used, focusing on surfaces susceptible to brittle fracture (e.g., Si (100), SiC (0001) Si-face).
- K_IC was measured using nanoindentation, calculating toughness from crack lengths induced by the indenter.
Grinding Wheel Fabrication:
- Five Back-Grinding Wheels (BGWs) were fabricated using a Cu-Sn matrix bond.
- Eb was controlled by varying Cobalt content from 10 wt% (BGW1, Eb=95.24 GPa) to 50 wt% (BGW5, Eb=131.38 GPa).
- Diamond parameters were fixed: median size 51.2 µm and concentration 12.5 vol%.
Grinding Process Parameters:
- Equipment: INSEMITEC IVG-3030 back-grinding machine.
- BGW Peripheral Speed: 23.5 m/s (Clockwise).
- Wafer Rotation Speed: 1.6 m/s (Opposite direction).
- Feed Rate: 0.5 µm/s.
- Material Removal: 200 µm total thickness removed per test.
Performance Measurement and Modeling:
- Diamond Protrusion Height (h_p): Measured using a confocal microscope.
- Grinding Load and MRR: Measured using an integrated tool dynamometer.
- Surface Roughness (Ra): Measured using an optical 3D surface profiler.
- Debris Analysis: Slurry collected, dried, and debris size measured via FE-SEM and image processing.
- SSD Assessment: Cross-sectional TEM analysis was performed on SiC wafers to measure internal crack lengths.
- Empirical Modeling: Weighted Least Squares (WLS) regression was used to fit the experimental data to the log-linear model linking h_p to Eb and K_IC.

Commercial Applications

The findings provide direct, actionable insights for optimizing high-throughput wafer thinning processes in the semiconductor industry.

High-Power Semiconductor Manufacturing:
- Application: Back grinding of Silicon Carbide (SiC) wafers for electric vehicle and renewable energy systems.
- Benefit: Enables high MRR (>740 µm/h) while maintaining zero observable SSD, crucial for device reliability in high-voltage applications.
Optoelectronics and Photonics:
- Application: Thinning of Sapphire (LED/Laser substrates) and Gallium Phosphide (GaP) wafers.
- Benefit: Allows precise control over surface quality (Ra) and subsurface damage by tailoring the grinding wheel Eb to the specific K_IC of the substrate.
Grinding Tool Design and Metallurgy:
- Application: Optimization of diamond wheel bond composition (Cobalt content in Cu-Sn matrix) for specific customer wafer types.
- Benefit: The h_p predictive model allows manufacturers to design wheels that maximize diamond retention and protrusion efficiency, extending wheel life and reducing dressing frequency.
Process Transfer and Optimization:
- Application: Rapidly establishing initial grinding parameters (feed/infeed) when transitioning between different wafer materials (e.g., Si to SiC).
- Benefit: Shortens the reliance on extensive Design of Experiments (DOE), reducing manufacturing costs and accelerating time-to-market for new semiconductor products.

View Original Abstract

Grinding semiconductor wafers with high hardness, such as SiC, remains a significant challenge due to the need to maximize material removal rates while minimizing subsurface damage. In the back-grinding process, two key parameters—the elastic modulus (Eb) of the grinding wheel bond and the fracture toughness (KIC) of the wafer—play a critical role in governing the behavior of diamond and the extent of wafer damage. This study systematically investigated the effect of Eb and KIC on diamond protrusion height (hp), surface roughness (Ra), grinding forces, and the morphology of generated debris. The study encompassed four wafer types—Si, GaP, sapphire, and ground SiC—using five Back-Grinding Wheels (BGWs), with Eb ranging from 95.24 to 131.38 GPa. A log-linear empirical relationship linking ℎₚ to Eb and KIC was derived and experimentally verified, demonstrating high predictive accuracy across all wafer-wheel combinations. Surface roughness (Ra) was measured in the range of 0.486 − 1.118𝜇m, debris size ranged from 1.41 to 14.74𝜇m, and the material removal rate, expressed as a thickness rate, varied from 555 to 1546𝜇m/h (equivalent to 75−209 mm³/min using an effective processed area of 81.07 cm²). For SiC, increasing the bond modulus from 95.24 to 131.38 GPa raised the average hp from 9.0 to 1.2 um; the removal rate peaked at 122.07 GPa, where subsurface damage (SSD) was minimized, defining a practical grindability window. These findings offer practical guidance for selecting grinding wheel bond compositions and configuring process parameters. In particular, applying a higher Eb is recommended for harder wafers to ensure sufficient diamond protrusion, while an appropriate dressing must be employed to prevent adverse effects from excessive stiffness. By balancing removal rate, surface quality, and subsurface damage constraints, the results support industrial process development. Furthermore, the protrusion model proposed in this study serves as a valuable framework for optimizing bond design and grinding conditions for both current and next-generation semiconductor wafers.

Tech Support

Original Source

DOI: https://doi.org/10.3390/ma18214890

References

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