Si/SiGe transistors for addressing large-scale qubit arrays for Quantum Computer

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Metadata	Details
Publication Date	2016-01-01
Authors	Gautham Rangasamy

Abstract

The use of quantum computer can dramatically increase the computation power when compared with a classical computer. This is achieved by the manipulation of qubits. Qubits are the basic unit of quantum computation, and assumes a superposition of the two classical states ’0’ and ’1’. Qubits can be realized in many ways, namely; Ion traps, Nitrogen vacancies in diamond, Transmons or Quantum dots. The implementation of confined single electron’s spin state in a quantum dot to encode quantum information, provides advantages of scalability and integration with current semiconductor process technology. These qubits are susceptible to en- vironmental influences, therefore to reduce it ( or to enhance the decoherence time), the system is kept at 20 mK. To maintain electron confinement in a quantum dot, the quantum dot is applied with specific voltages with stringent resolution conditions. (-2V to 2V with ± 5 µV resolution). Currently, this condition is met by using chemical batteries, which being large in size, affect the scalability of the system. To that end, use of analog and digital circuits to supply the confinement voltage and to address the qubit system can improve the scalability. Circuits which can be monolithically integrated with the qubit would reduce fabrication complexity and provide higher operation speed as well. Thereby, this thesis studies whether MOSFETs can be formed using the same wafer substrate of quantum dots. In this thesis, the research of a fabrication recipe for MOSFETs based on strained Si in SiGe-Si-SiGe heterostructure is presented. To maintain the strain in Si, the process temperature should not exceed 700 ◦ C. This is confirmed with Raman spectroscopy experiments. Then the MOSFETs are fabricated and characterized in room and cyro-temperatures (4K). The SiGe transistor has following parameters at 4K : mobility, µ ( 1980 cm 2 / Vs), transconductance (30.7 µS), I on (210 −5 A), I off (210 −12 A) and sub-threshold slope (80 mV/dec). Using it, a rudimentary SPICE model of the SiGe MOSFETs are derived and then the addressing of qubit system using Demux architectures of Static CMOS, Pass Transistor, Transmission and Binary Tree are studied. From the timing and power analysis, Binary Tree architecture was found to be best choice as it provides the lowest static power consumption of 66.5 nW for 1 to 1024 Demux. To improve the device characteristics, high k dielectric materials were studied. To study the feasibility of high k dielectrics, MOS capacitors were fabricated using ALD deposition for Al 2 O 3 , SiO 2 and HfO 2 . The defect densities were obtained by comparing the theoretical and experimental high frequency voltage and capacitance curves. From the current voltage curves, the breakdown field strength and resistivity is extracted. ALD Alumina of 7nm stacked on top of Silicon dioxide of 3nm has the least influence from charge defect with Fixed Oxide charges of 1.210 12 eV −1 cm −2 and Interface charges of 9.110 11 eV −1 cm −2 . Also, this stacked oxide provides a gate resistance of 111 GΩ, thereby making it the best candidate for gate dielectric.

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