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6CCVD Research

Improve Chip Side Wall Crack Issue in Nanometer Packing Process of Semiconductor

At a Glance

Section titled ā€œAt a Glanceā€
MetadataDetails
Publication Date2020-12-03
JournalIEEE Transactions on Components Packaging and Manufacturing Technology
AuthorsChiaā€Nan Wang, Ming-Hsien Hsueh, Chao-Jung Lai, Chih-Chao Chung, Wenā€Chung Chen
InstitutionsNational Pingtung University of Science and Technology, Advanced Semiconductor Engineering (Taiwan)
Citations6

Abstract

Section titled ā€œAbstractā€

The chip side wall crack of semiconductor nanometer packaging process has always been an important technological problem that the global semiconductor packaging industry needs to overcome. This research has helped the worldā€™s biggest semiconductor package factory to improve the chip side wall crack issue faced by nanometer wafer packaging process, thus enhancing its yield rate. After analyzing the abnormality of nanometer wafer packaging process, this research team found that the chip side wall crack problem was caused by a poor laser waveform during the laser cutting process, resulting in debris along the chip side wall. Subsequently, as the diamond cutter cuts into the chip in the following process, the cutter impacts the debris which then impacts the side wall resulting in a side wall crack. The Teoriya Resheniya Izobreatatelskikh Zadatch (TRIZ) analysis was used to deduce a suitable improvement method. After applying the TRIZ analysis, this research team confirmed that by modifying the laser equipment to create a more uniform laser waveform, the diamond cutter was able to achieve a clean cut of the chip without impacting debris and thus significantly decreased the chip side wall crack occurrences. The shipment yield rate was increased from 92.8% to 99.61% as a result of the teamā€™s modifications.

Tech Support

Section titled ā€œTech Supportā€

Original Source

Section titled ā€œOriginal Sourceā€

References

Section titled ā€œReferencesā€
  1. 2014 - Multi beam laser grooving process parameter development and die strength characterization for 40 nm node low-K/ULK wafer
  2. 2008 - Laser grooving process development for low-k/ultra low-k devices
  3. 2017 - Applying TRIZ instructional strategies to vocational students’ imaginative learning and practice

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