Over 50 mA Current in Interdigitated Diamond Field Effect Transistor
At a Glance
Section titled âAt a Glanceâ| Metadata | Details |
|---|---|
| Publication Date | 2024-09-03 |
| Journal | IEEE Electron Device Letters |
| Authors | Damien Michez, Juliette Letellier, Imane Hammas, Julien Pernot, Nicolas Rouger |
| Institutions | Centre National de la Recherche Scientifique, Institut polytechnique de Grenoble |
| Citations | 4 |
| Analysis | Full AI Review Included |
Executive Summary
Section titled âExecutive SummaryâThis letter reports the highest total current achieved to date for a bulk diamond Field Effect Transistor (FET), utilizing an interdigitated Junction FET (JFET) architecture to drastically scale performance.
- Record Current Achievement: The device demonstrated a total current exceeding 50 mA at VDS = -15 V, VGS = 0 V, and 450 K (177 °C), setting a new benchmark for bulk diamond FETs.
- Architecture Scaling: Performance was achieved by implementing an interdigitated architecture comprising 24 parallel fingers, resulting in a large total gate width of 14.7 mm.
- Specific Performance: The specific ON-resistance (RON.S) was measured at 608 mΩ.cm2, with a threshold voltage (Vth) of 50 V at 450 K.
- Material Quality Validation: The use of homogeneous, large-size diamond layers grown by Chemical Vapor Deposition (CVD) validates the maturity of diamond material for complex, scaled power devices.
- Performance Limiter Identified: High-temperature measurements indicate that the device access resistance (primarily the heavily boron-doped p++ layer bottleneck), rather than the conduction channel resistance, is the predominant factor limiting current.
- Operational Requirement: As a JFET built on an n-doped substrate, the device requires illumination (11 mW/cm2 white LED) to ionize nitrogen donors (1.7 eV activation energy) and modulate the pn junctionâs space charge region (SCR).
Technical Specifications
Section titled âTechnical Specificationsâ| Parameter | Value | Unit | Context |
|---|---|---|---|
| Peak Drain Current (ID) | > 50 | mA | VDS = -15 V, VGS = 0 V, 450 K |
| Specific ON-Resistance (RON.S) | 608 | mΩ.cm2 | Measured at 450 K |
| Total Gate Width (WG) | 14.7 | mm | 24 parallel fingers (24 x 614 ”m) |
| Threshold Voltage (Vth) | 50 | V | Measured at 450 K |
| p-layer Resistivity (Channel) | 1.52 | Ω.cm | 2x1017 cm-3 B-doped layer, 450 K |
| p++ layer Resistivity (Ohmic) | 3.6 | mΩ.cm | Heavily B-doped layer (> 3x1020 cm-3), 450 K (TLM) |
| p-layer Thickness | 350 | nm | Conduction channel |
| p++ layer Thickness | 280 | nm | Ohmic contact layer |
| Substrate Type | HPHT (100) n-type | - | Nitrogen concentration approx 1019 cm-3 |
| Nitrogen Activation Energy (EA) | 1.7 | eV | Requires illumination for ionization |
| Maximum Electric Field (Junction) | 5 | MV/cm | 1D simulation (Vext = 140 V) |
| Operating Temperature Range | 299 to 523 | K | Characterization range |
Key Methodologies
Section titled âKey MethodologiesâThe interdigitated JFET was fabricated using advanced CVD growth and etching techniques on a High Pressure High Temperature (HPHT) substrate.
- Substrate and Channel Growth:
- A 500 ”m thick (100) HPHT diamond substrate (n-doped, N concentration approx 1019 cm-3) was used.
- A 350 nm p-doped channel layer (target B concentration = 2x1017 cm-3) was grown via Microwave Plasma Enhanced Chemical Vapor Deposition (MPCVD).
- Mesa Structure Definition:
- Reactive Ion Etching (RIE) using O2/CF4 plasma was performed to mesa-structure the p-layer, confining the current and ensuring electrical insulation between the 24 parallel fingers.
- Ohmic Contact Layer:
- A 280 nm heavily boron-doped (p++) layer (target B concentration > 3x1020 cm-3) was obtained by selective MPCVD growth to facilitate low-resistance ohmic contacts.
- Metallization and Annealing:
- A Ti/Pt/Au (30/40/50 nm) tri-metal multilayer was deposited for drain, source, and gate contacts.
- The device was annealed at 600 °C for 1 hour to promote Titanium Carbide (TiC) bonding and reduce contact resistance.
- Surface Treatment:
- An ozone plasma treatment was performed using a Xenon EXCIMER UV lamp (172 nm) under 500 mbar oxygen pressure to achieve oxygen termination, eliminating parasitic surface currents.
- Electrical Characterization:
- Measurements were conducted in a probe station under vacuum (approx 10-4 mbar) across a temperature range (299 K to 523 K).
- An 11 mW/cm2 white LED source was used to provide the necessary photon energy (greater than 1.7 eV, less than 5.5 eV) to ionize the nitrogen donors in the substrate, enabling gate control.
Commercial Applications
Section titled âCommercial ApplicationsâThe demonstration of high-current, scaled diamond FETs operating at elevated temperatures directly addresses critical needs in the power electronics sector.
- High-Power Switching Modules: The ability to scale total current via interdigitation makes this technology suitable for high-power modules (e.g., 1200 V or higher class) where silicon carbide (SiC) and gallium nitride (GaN) are currently dominant.
- Aerospace and Transportation (EVs): As supported by the European DCADE project (Clean Sky 2 JU), these devices are crucial for developing high-efficiency, high-density power converters required in electric vehicles and aircraft, where weight and thermal management are critical.
- High-Temperature Industrial Electronics: Diamondâs superior thermal conductivity (2200-2400 W.m-1.K-1) combined with the deviceâs stable operation at 450 K allows deployment in harsh environments where conventional silicon devices fail.
- Next-Generation Power Management: The unique characteristic of diamond bulk FETsâdecreasing resistance with increasing temperature due to impurity ionizationâoffers a novel efficiency/power density trade-off compared to other wide bandgap materials.
- Optimization of Access Resistance: The finding that access resistance limits performance provides a clear roadmap for commercial optimization, specifically by redesigning or removing the p++ layer bottleneck.
View Original Abstract
This letter presents the bulk diamond field-effect transistor (FET) with the\nhighest current value reported at this moment. The goal was to drastically\nincrease the current of this type of device by increasing the total gate width\nthanks to an interdigitated architecture and homogeneous growth properties. We\nreport the results obtained by fabricating and characterizing an interdigitated\njunction FET (JFET). The device develops a total gate width of 14.7 mm, with 24\nparalleled fingers and a current higher than 50 mA at VDS = -15 V, VGS = 0 V,\nat 450 K and under illumination which is the highest value reported for a bulk\ndiamond FET. Its specific ON-resistance and threshold voltage are respectively\n608 m$\Omega$.cm${}^2$, 50 V. From Transfer length method (TLM) measurements we\nextract a resistivity of 3.6 m$\Omega$.cm for a heavily boron-doped\n(p++)-diamond layer and 1.52 $\Omega$.cm for a 2.1017 cm-3 p-doped diamond\nlayer at 450 K. We measured the drain current versus gate voltage\ncharacteristics at high temperature showing that it is no longer the conduction\nchannel resistance but the device access resistance that is predominant. This\nstudy indicates that it is possible to drastically improve the ON-state of FETs\nby using an interdigitated architecture, while using homogeneous large size\ndiamond layers grown by CVD.\n