Surface and subsurface microstructure properties of monocrystalline silicon cut by electroplated diamond wire saw
At a Glance
Section titled âAt a Glanceâ| Metadata | Details |
|---|---|
| Publication Date | 2025-09-28 |
| Journal | Surface Science and Technology |
| Authors | Dong Hui, Yufei Gao, Chunfeng Yang |
| Institutions | Shandong University, Shandong Jiaotong University |
| Analysis | Full AI Review Included |
Executive Summary
Section titled âExecutive SummaryâThis study experimentally investigates the surface and subsurface integrity of monocrystalline silicon (mono-Si) wafers sliced using an electroplated diamond wire saw (DWS), focusing on optimizing process parameters for high-quality substrates.
- Material Removal Mechanism: Wafer surface generation is characterized by a mixed brittle/ductile removal mode, resulting in both slender ductile grooves and deep brittle pits, alongside periodic wavy saw marks.
- Key Quality Indicators: Saw mark Peak-Valley (PV) values (ranging 2.6 to 5.3 ”m) and Subsurface Damage (SSD) depth (ranging 11.2 to 22.8 ”m) were measured and analyzed. SSD is primarily caused by residual median cracks propagating inward.
- Dominant Parameter: Feed speed (Vf) was identified as the parameter with the greatest impact on both PV value and SSD depth, followed by specimen length (L), and then wire speed (Vs).
- Optimization Strategy: To minimize PV and SSD, engineers should prioritize increasing wire speed (Vs) and decreasing both specimen feed speed (Vf) and specimen length (L).
- Microcrack Characteristics: Subsurface damage includes residual median cracks (determining SSD depth) and lateral cracks that have not fully expanded to remove material.
- Practical Impact: The findings provide an experimental basis for optimizing DWS parameters to improve wafer quality, reduce post-slicing processing costs, and increase product yield in photovoltaic and microelectronics manufacturing.
Technical Specifications
Section titled âTechnical Specificationsâ| Parameter | Value | Unit | Context |
|---|---|---|---|
| Core Wire Diameter | 120 | ”m | Diamond wire specification |
| Envelope Diameter | 160 | ”m | Diamond wire specification |
| Abrasive Type | Electroplated | Diamond | Abrasive coating type |
| Abrasive Size | 15-20 | ”m | Abrasive particle diameter |
| Abrasive Density | 120-130 | grits/mm2 | Abrasive distribution on wire |
| Specimen Feed Speed (Vf) Range | 0.6 to 1.2 | mm/min | Single factor test range |
| Diamond Wire Speed (Vs) Range | 60 to 120 | m/min | Single factor test range |
| Saw Mark Waviness (PV) Range | 1.5 to 5.3 | ”m | Overall experimental range |
| Subsurface Damage (SSD) Range | 7 to 22.8 | ”m | Overall experimental range |
| SSD Etching Solution Ratio | 200:200:30 | ml:ml:g | H2O:HF (49%):CrO3 |
| Critical Cutting Depth (Ductile) | Varies | ”m | Determines brittle-ductile transition |
Key Methodologies
Section titled âKey Methodologiesâ- Slicing Setup: Monocrystalline silicon specimens were sliced using a reciprocating single diamond wire saw device (WXD170).
- Experimental Design: Experiments utilized both single-factor variation (Vf, Vs, L) and an L9(33) orthogonal array design to evaluate parameter influence and interaction.
- Surface Topography Measurement: A Keyence laser confocal microscope (VK-X200K) was used to capture 2D and 3D surface morphology and measure saw mark waviness PV values.
- SSD Specimen Preparation: Sliced wafers were mounted and inlaid into a specimen holder, followed by lapping and polishing to expose the thickness cross-section.
- Microcrack Visualization: The polished cross-sections were subjected to corrosion using an acidic solution (H2O:HF 49%:CrO3) to reveal subsurface microcracks.
- SSD Quantification: SSD depth was measured as the maximum propagation distance of the median cracks from the newly formed surface inward into the material.
- Influence Analysis: Range analysis (R values) was applied to the orthogonal experimental data to rank the primary and secondary influence of Vf, Vs, and L on PV and SSD.
Commercial Applications
Section titled âCommercial ApplicationsâThis research directly supports manufacturing processes in industries reliant on high-quality silicon wafers:
- Photovoltaic (PV) Manufacturing: Optimizing the slicing of mono-Si crystal rods for solar cell substrates. Reduced SSD minimizes material loss during subsequent texturization processes, lowering manufacturing costs.
- Microelectronic Device Fabrication: Producing high-integrity mono-Si wafers for Integrated Circuit (IC) chips. Minimal SSD is crucial as subsurface defects can severely compromise device performance and yield.
- Advanced Materials Processing: The methodology and findings regarding brittle-ductile transition and crack propagation are applicable to the precision slicing of other hard, brittle materials, including sapphire, SiC, and magnetic materials (e.g., NdFeB).
- Wire Saw Machine Development: Providing data necessary for manufacturers to design and calibrate next-generation DWS machines capable of stable operation at higher wire speeds and feed rates, meeting the industry trend toward larger wafer sizes and finer wires.