Fundamental Cooling Limits for High Power Density Gallium Nitride Electronics
At a Glance
Section titled āAt a Glanceā| Metadata | Details |
|---|---|
| Publication Date | 2015-06-01 |
| Journal | IEEE Transactions on Components Packaging and Manufacturing Technology |
| Authors | Yoonjin Won, Jungwan Cho, Damena Agonafer, Mehdi Asheghi, Kenneth E. Goodson |
| Institutions | Stanford University |
| Citations | 143 |
Abstract
Section titled āAbstractāThe peak power density of GaN high-electron-mobility transistor technology is limited by a hierarchy of thermal resistances from the junction to the ambient. Here, we explore the ultimate or fundamental cooling limits for junction-to fluid cooling, which are enabled by advanced thermal management technologies, including GaN-diamond composites and nanoengineered heat sinks. Through continued attention to near-junction resistances and extreme flux convection heat sinks, heat fluxes beyond 300 kW/cm <sup xmlns:mml=āhttp://www.w3.org/1998/Math/MathMLā xmlns:xlink=āhttp://www.w3.org/1999/xlinkā>2</sup> from individual 2-Ī¼m gates and 10 kW/cm2 from the transistor footprint will be feasible. The cooling technologies under discussion here are also applicable to thermal management of 2.5-D and 3-D logic circuits at lower heat fluxes.