Diamond-shaped Ge and Ge0.9Si0.1 gate-all-around nanowire FETs with four {111} facets by dry etch technology
At a Glance
Section titled “At a Glance”| Metadata | Details |
|---|---|
| Publication Date | 2015-12-01 |
| Authors | Yao‐Jen Lee, Fu-Ju Hou, Shang-Shiun Chuang, Fu-Kuo Hsueh, Kuo-Hsing Kao |
| Institutions | National Cheng Kung University, National Yang Ming Chiao Tung University |
| Citations | 22 |
Abstract
Section titled “Abstract”We propose a feasible pathway to scale the Ge MOSFET technology by using a novel diamond-shaped Ge and Ge <sub xmlns:mml=“http://www.w3.org/1998/Math/MathML” xmlns:xlink=“http://www.w3.org/1999/xlink”>09</sub> Si <sub xmlns:mml=“http://www.w3.org/1998/Math/MathML” xmlns:xlink=“http://www.w3.org/1999/xlink”>01</sub> gate-all-around (GAA) nanowire (NW) FETs with four {111} facets. The device fabrication requires only simple top-down dry etching and blanket Ge epitaxy techniques readily available in mass production. The proposed dry etching process involves three isotropic/anisotropic etching steps with different Cl <sub xmlns:mml=“http://www.w3.org/1998/Math/MathML” xmlns:xlink=“http://www.w3.org/1999/xlink”>2</sub> /HBr ratios for forming the suspended diamond-shaped channel. Taking advantages of the GAA configuration, favorable carrier mobility of the {111} surface, nearly defect-free suspended channel, and improved dopant activation by incorporating Si, nFET and pFET with excellent performance have been demonstrated, including an I <sub xmlns:mml=“http://www.w3.org/1998/Math/MathML” xmlns:xlink=“http://www.w3.org/1999/xlink”>on</sub> /I <sub xmlns:mml=“http://www.w3.org/1998/Math/MathML” xmlns:xlink=“http://www.w3.org/1999/xlink”>off</sub> ratio exceeding 10 <sup xmlns:mml=“http://www.w3.org/1998/Math/MathML” xmlns:xlink=“http://www.w3.org/1999/xlink”>8</sup> , the highest ever reported for Ge-based pFETs.
Tech Support
Section titled “Tech Support”Original Source
Section titled “Original Source”References
Section titled “References”- 2012 - Triangular-channel Ge NFETs on Si with (111) Sidewall-Enhanced Ion and Nearly Defect-free Channels
- 2011 - Nearly Defect-free Ge Gate-All-Around FETs on Si Substrates
- 2009 - CMOS Compatible Ge/Si Core/Shell Nanowire Gate-All-Around pMOSFET Integrated with HfO2/TaN Gate Stack