High Voltage Stress Induced in Transparent Polycrystalline Diamond Field-Effect Transistor and Enhanced Endurance Using Thick Al2O3Passivation Layer
At a Glance
Section titled “At a Glance”| Metadata | Details |
|---|---|
| Publication Date | 2017-03-20 |
| Journal | IEEE Electron Device Letters |
| Authors | Mohd Syamsul, Y. Kitabayashi, Takuya Kudo, Daisuke Matsumura, Hiroshi Kawarada |
| Institutions | Waseda University |
| Citations | 26 |
Abstract
Section titled “Abstract”A transparent polycrystalline diamond field-effect transistor (FET) was fabricated and measured in room temperature measurements, which reveals comparatively high maximum current density and high breakdown voltage of more than 1000 V. A harsh stress environment is proposed for simple and time-effective reliability stress measurement of the FET using a method of 50 continuous cycles of 500-V voltage stress. A 400-nm-thick Al <sub xmlns:mml=“http://www.w3.org/1998/Math/MathML” xmlns:xlink=“http://www.w3.org/1999/xlink”>2</sub> O <sub xmlns:mml=“http://www.w3.org/1998/Math/MathML” xmlns:xlink=“http://www.w3.org/1999/xlink”>3</sub> counter-destructive passivation layer was implemented on the FET for the stress measurements. Devices with wide gate-drain length (L <sub xmlns:mml=“http://www.w3.org/1998/Math/MathML” xmlns:xlink=“http://www.w3.org/1999/xlink”>GD</sub> ) retain their FET characteristics after the harsh stress measurements by only 50% reductions maximum current density.