Heterogeneous integration process development and testing of light-emitting transistors
At a Glance
Section titled āAt a Glanceā| Metadata | Details |
|---|---|
| Publication Date | 2019-05-01 |
| Journal | Illinois Digital Environment for Access to Learning and Scholarship (University of Illinois at Urbana-Champaign) |
| Authors | Coleman Williams |
Abstract
Section titled āAbstractāHeterogeneous integration of III-V material, accomplished via a metal-eutectic bond, followed by fabrication of three-terminal photonic devices, allows for the possibility of forming electronic-photonic integrated circuitry. Before bonding III-V material to silicon, it is necessary to thin the III-V material such that the process remains CMOS compatible. When using a temporary bonding polymer prior to integration, wet etching is not a viable option to remove the bulk substrate as the polymer is also etched. A process composed of diamond- and alumina-based lapping in combination with chemo-mechanical polishing is developed to remove the bulk substrate. \nCurrent research aims to use light-emitting transistors (LETs) on heterogeneously integrated III-V epitaxial material as the foundation for photonic logic circuits. Before this is done, fabricated monolithic LETs are characterized. Different designs are used such that different device structures may be compared. This characterization provides insights which may serve not only as a guide for fabrication of integrated LETs but as a baseline against which the integrated LETs may be compared.
Tech Support
Section titled āTech SupportāOriginal Source
Section titled āOriginal Sourceā- DOI: None