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6CCVD Research

Optimization of Semiconductor Device Packaging Singulation Process

At a Glance

Section titled ā€œAt a Glanceā€
MetadataDetails
Publication Date2019-06-01
JournalIOP Conference Series Materials Science and Engineering
AuthorsWei Tong, Mohd Nazri Mahmud
InstitutionsUniversiti Sains Malaysia
Citations5

Abstract

Section titled ā€œAbstractā€

Abstract With the advancement of semiconductor technology, the assembly process of semiconductor packaging is driving the devices to become smaller and smaller in size. One of the critical processes in backend assembly is the productā€™s singulation to separate bulk processed products into individual unit. Before the sawing process kick-off, saw blade preparation (blade dressing) has to be performed. Blade dressing is the process of sharpening the saw blade surface to expose the diamond grits to the blade surface that are covered by the blade bonding material (Nickel-based). Inappropriate blade preparation technique induces burn mark defect to semiconductor devices. This research presented the dressing process optimization on critical factors using Silicon carbide (SiC) as part of the effort to enhance the product quality. The 2 k Full Factorial Design of Experiment (DOE) methodology, with consideration of three factors namely Blade Revolution Per Minute (RPM), Feedspeed and Dress Pass. The overall singulation process yields performance improvement by reducing the burn mark to < 0.1% with optimum saw blade preparation technique. Besides, the optimized process complementarily contributes to less kerf deformation and dressing wear.

Tech Support

Section titled ā€œTech Supportā€

Original Source

Section titled ā€œOriginal Sourceā€

References

Section titled ā€œReferencesā€
  1. 2001 - Overview of recent developments in microelectronic packaging
  2. 2018 - Enabling information age through advanced packaging technologies and electronic materials
  3. 2011 - Developments of blade dressing technique using SiC board for C90 low-k wafer sawing
  4. 2012 - Self-adaptive phosphor coating technology for white LED packaging [Crossref]
  5. 2010 - Chipping free process for combination of narrow saw street (60um) and thick wafer (600um) sawing process
  6. 2013 - Evaluation of silicon fracture strength dependence on stealth dicing layers for ā€˜cleave-before-useā€™ MEMS freestanding cantilever probes
  7. 2004 - Basic Mechanisms and Models of Multi-Wire Sawing [Crossref]
  8. 2017 - Plasma Dicing Fully Integrated Process-Flows Suitable for BEOL Advanced Packaging Fabrications

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