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Tightly Stacked 3D Diamond-Shaped Ge Nanowire Gate-All-Around FETs With Superior nFET and pFET Performance

MetadataDetails
Publication Date2021-11-04
JournalIEEE Electron Device Letters
AuthorsYi-Wen Lin, Hao‐Hsiang Chang, Y.W. Huang, Chong-Jhe Sun, Siao-Cheng Yan
InstitutionsTaiwan Semiconductor Manufacturing Company (Taiwan), National Tsing Hua University
Citations11

We propose that the use of tightly stacked three-dimensional (3D) diamond-shaped Ge nanowire (NW) gate-all-around field-effect transistor (Ge-NW GAAFET) is a feasible approach to continuous scaling. The proposed devices with the Al<sub>2</sub>O<sub>3</sub> dielectric exhibit high I<sub>SAT</sub> of 1200 <inline-formula> <tex-math notation=“LaTeX”>$\boldsymbol {\mu } \text{A}/\boldsymbol {\mu } \text{m}$ </tex-math></inline-formula> (pFET) and 1100 <inline-formula> <tex-math notation=“LaTeX”>$\boldsymbol {\mu } \text{A}/\boldsymbol {\mu } \text{m}$ </tex-math></inline-formula> (nFET), high I<sub>ON</sub>/I<sub>OFF</sub> ratio of approximately <inline-formula> <tex-math notation=“LaTeX”>${1} \times {10}^{{5}}$ </tex-math></inline-formula>, and steep subthreshold swing (SS) close to 70mV/dec. Superior gate control of the Ge-NW GAAFET was confirmed by the 3D TCAD simulation for the sub-3nm node applications. The formation of the tightly stacked Ge NWs is fully compatible with the complementary metal oxide semiconductor (CMOS) technology platform using only alternating isotropic and anisotropic dry etching, thus showing promising potential for extending CMOS scaling in the vertical direction.

  1. 2014 - In-situ doped and tensily stained Ge junctionless gate-all-around nFETs on SOI featuring $\text{I}{on}$ =$828~\mu\text{A}/\mu\text{m}$ , $\text{I}{on}/\text{I}_{off}$ &#x02DC;$1\times10^{5}$ , DIBL=16-54 mV/V, and 1.4X external strain enhancement