Interlayer Engineering to Achieve <1 m2K/GW Thermal Boundary Resistances to Diamond for Effective Device Cooling
At a Glance
Section titled āAt a Glanceā| Metadata | Details |
|---|---|
| Publication Date | 2023-12-09 |
| Authors | Kelly Woo, Mohamadali Malakoutian, Younghun Jo, Xiang Zheng, Tom Pfeifer |
| Institutions | At Bristol, The University of Texas at Dallas |
| Citations | 10 |
Abstract
Section titled āAbstractāHighly localized electric fields and resulting high-temperature spots can cause channel performance degradation in semiconductor devices, which eventually leads to premature failure due to thermal runaway. To address these challenges, well-designed thermal management at the device/chip level is crucial. Diamond due to its high thermal conductivity is an effective heat-spreader when integrated near the hot spot in the channel/junction. However, a significant bottleneck lies in the thermal boundary resistance (TBR) between the hot spot generated in the device and the heat spreader. Here, atomistic thermal transport modeling was first used to show the reduction of TBR below the diffuse-mismatch (DMM) theory predictions is possible with a thin SiC interlayer. Then, experimentally, the SiC interlayer crystallinity and thickness were engineered to produce TBRs of 3.1Ā±0.7 and 1.89Ā±0.18 m <sup xmlns:mml=āhttp://www.w3.org/1998/Math/MathMLā xmlns:xlink=āhttp://www.w3.org/1999/xlinkā>2</sup> K/GW. TBRs in this range, alone can lead to W-band power to > 30 W/mm in GaN HEMTs. Such low TBR would lead to greater reliability and performance for both GaN and Si technologies.