Design Technology Co-Optimization for Gate-All-Around Nanosheet Transistors Considering Source/Drain Confinement and Post- Gate Single Diffusion Break
At a Glance
Section titled “At a Glance”| Metadata | Details |
|---|---|
| Publication Date | 2024-05-27 |
| Journal | IEEE Transactions on Electron Devices |
| Authors | Dawei Wang, Tao Liu, Xin Sun, Ziqiang Huang, Lewen Qian |
| Institutions | Shanghai Innovative Research Center of Traditional Chinese Medicine, Shanghai Fudan Microelectronics (China) |
| Citations | 8 |
Abstract
Section titled “Abstract”In this work, a novel self-aligned source/drain confinement (SA-SDC) scheme is proposed to enable the downsizing of gate-all-around (GAA) nanosheet (NS) field-effect transistors (FETs). Compared with the traditional diamond-shaped source/drain (S/D) epitaxy, the proposed SA-SDC scheme suppresses the lateral over expansion and facilitates wrap-around contact (WAC) formation, resulting in the decrease of device area, parasitic capacitance ( <inline-formula xmlns:mml=“http://www.w3.org/1998/Math/MathML” xmlns:xlink=“http://www.w3.org/1999/xlink”> <tex-math notation=“LaTeX”>$\textit{C}{\text{para}}$</tex-math> </inline-formula> ), and resistance ( <inline-formula xmlns:mml=“http://www.w3.org/1998/Math/MathML” xmlns:xlink=“http://www.w3.org/1999/xlink”> <tex-math notation=“LaTeX”>$\textit{R}{\text{para}}$</tex-math> </inline-formula> ). A calibrated 3-D TCAD simulation demonstrates a 35% reduction in the device <italic xmlns:mml=“http://www.w3.org/1998/Math/MathML” xmlns:xlink=“http://www.w3.org/1999/xlink”>RC</i> delay for the SA-SDC NS FET. Considering various device structures and channel stress variations induced by diffusion break integration schemes, a comprehensive investigation of the 15-stage ring oscillator (RO) is conducted. By integrating the stress-enhanced postgate single diffusion break (PG-SDB) process, the SA-SDC NAND2 cell achieves an additional 21% reduction in the power dissipation or a 9% increase in the frequency. Power, performance, and area (PPA) are also collaboratively optimized for different applications using the quantitative quality factor. Particularly, the NAND2 cell is optimized within the constrained footprint. The cell, with 30-40-nm NS width of the n-type device, exhibits the optimal and robust performance for all the simulated technology/design options.
Tech Support
Section titled “Tech Support”Original Source
Section titled “Original Source”References
Section titled “References”- 2020 - A reliability enhanced 5 nm CMOS technology featuring 5th generation FinFET with fully-developed EUV and high mobility channel for mobile SoC and high performance computing application
- 2019 - 5 nm CMOS production technology platform featuring full-fledged EUV, and high mobility channel FinFETs with densest 0.021 μm2 SRAM cells for mobile SoC and high performance computing applications